clk: tegra: Fixes for MBIST work around
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Message ID 1532010323-28534-1-git-send-email-pdeschrijver@nvidia.com
State New
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Series
  • clk: tegra: Fixes for MBIST work around
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Commit Message

Peter De Schrijver July 19, 2018, 2:25 p.m. UTC
From: Joseph Lo <josephl@nvidia.com>

Fix some incorrect data in LVL2 offset and bit mask.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-tegra210.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Jon Hunter July 19, 2018, 3:25 p.m. UTC | #1
On 19/07/18 15:25, Peter De Schrijver wrote:
> From: Joseph Lo <josephl@nvidia.com>
> 
> Fix some incorrect data in LVL2 offset and bit mask.

Fixes tag?
 
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index d92f1d7..e71a9ce 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -2603,7 +2603,7 @@ struct utmi_clk_param {
>  	[TEGRA_POWERGATE_MPE] = {
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
>  		.lvl2_offset = LVL2_CLK_GATE_OVRE,
> -		.lvl2_mask = BIT(2),
> +		.lvl2_mask = BIT(29),
>  	},
>  	[TEGRA_POWERGATE_SOR] = {
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> @@ -2654,14 +2654,14 @@ struct utmi_clk_param {
>  		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
>  		.clk_init_data = nvdec_slcg_clkids,
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> -		.lvl2_offset = LVL2_CLK_GATE_OVRC,
> +		.lvl2_offset = LVL2_CLK_GATE_OVRE,
>  		.lvl2_mask = BIT(9) | BIT(31),
>  	},
>  	[TEGRA_POWERGATE_NVJPG] = {
>  		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
>  		.clk_init_data = nvjpg_slcg_clkids,
>  		.handle_lvl2_ovr = tegra210_generic_mbist_war,
> -		.lvl2_offset = LVL2_CLK_GATE_OVRC,
> +		.lvl2_offset = LVL2_CLK_GATE_OVRE,
>  		.lvl2_mask = BIT(9) | BIT(31),
>  	},
>  	[TEGRA_POWERGATE_AUD] = {

Otherwise looks good to me. 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Cheers
Jon

Patch
diff mbox series

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index d92f1d7..e71a9ce 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2603,7 +2603,7 @@  struct utmi_clk_param {
 	[TEGRA_POWERGATE_MPE] = {
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
 		.lvl2_offset = LVL2_CLK_GATE_OVRE,
-		.lvl2_mask = BIT(2),
+		.lvl2_mask = BIT(29),
 	},
 	[TEGRA_POWERGATE_SOR] = {
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
@@ -2654,14 +2654,14 @@  struct utmi_clk_param {
 		.num_clks = ARRAY_SIZE(nvdec_slcg_clkids),
 		.clk_init_data = nvdec_slcg_clkids,
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
-		.lvl2_offset = LVL2_CLK_GATE_OVRC,
+		.lvl2_offset = LVL2_CLK_GATE_OVRE,
 		.lvl2_mask = BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_NVJPG] = {
 		.num_clks = ARRAY_SIZE(nvjpg_slcg_clkids),
 		.clk_init_data = nvjpg_slcg_clkids,
 		.handle_lvl2_ovr = tegra210_generic_mbist_war,
-		.lvl2_offset = LVL2_CLK_GATE_OVRC,
+		.lvl2_offset = LVL2_CLK_GATE_OVRE,
 		.lvl2_mask = BIT(9) | BIT(31),
 	},
 	[TEGRA_POWERGATE_AUD] = {