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[v3,24/40] target/mips: Add updating BadInstr and BadInstrP registers for nanoMIPS

Message ID 1532004912-13899-25-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Updating BadInstr and BadInstrP registers was addded for nanoMIPS.
BadInstr and BadInstrP support for pre-nanoMIPS remains
unimplemented.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 target/mips/helper.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Comments

Richard Henderson July 23, 2018, 4:36 p.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> +        if (!(env->insn_flags & ISA_NANOMIPS32)) {
> +            /* TODO: add BadInstr support for pre-nanoMIPS */
> +             return;
> +        }
> +        if (env->CP0_Config3 & (1 << CP0C3_BI)) {
> +            instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
> +            if ((env->insn_flags & ISA_NANOMIPS32) &&

Redundant check for nanomips.


r~
Aleksandar Markovic July 24, 2018, 10:47 a.m. UTC | #2 
> From: Stefan Markovic <stefan.markovic@rt-rk.com>
> Sent: Thursday, July 19, 2018 2:54 PM
> Subject: [PATCH v3 24/40] target/mips: Add updating BadInstr and BadInstrP registers for nanoMIPS
>
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Updating BadInstr and BadInstrP registers was addded for nanoMIPS.
> BadInstr and BadInstrP support for pre-nanoMIPS remains
> unimplemented.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> ---
>  target/mips/helper.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index e215af9..5299f21 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -683,7 +683,28 @@ static void set_hflags_for_handler (CPUMIPSState *env)
>  static inline void set_badinstr_registers(CPUMIPSState *env)
>  {
>      if (env->hflags & MIPS_HFLAG_M16) {
> -        /* TODO: add BadInstr support for microMIPS */
> +        uint32_t instr;
> +        if (!(env->insn_flags & ISA_NANOMIPS32)) {
> +            /* TODO: add BadInstr support for pre-nanoMIPS */
> +             return;
> +        }
> +        if (env->CP0_Config3 & (1 << CP0C3_BI)) {
> +            instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
> +            if ((env->insn_flags & ISA_NANOMIPS32) &&
> +                ((instr & 0x10000000) == 0)) {
> +                instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
> +            }
> +            env->CP0_BadInstr = instr;
> +        }
> +        if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
> +            (env->hflags & MIPS_HFLAG_BMASK)) {
> +            if (!(env->hflags & MIPS_HFLAG_B16)) {
> +                env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
> +            } else {
> +                env->CP0_BadInstrP =
> +                    (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16;
> +            }
> +        }
>          return;
>      }
>      if (env->CP0_Config3 & (1 << CP0C3_BI)) {
> --
> 2.7.4

This new block should be placed before MIPS_HFLAG_M16 check. The whole patch should be merged with the succeeding patch, as noted in other reviews.

Aleksandar
diff mbox series

Patch

diff --git a/target/mips/helper.c b/target/mips/helper.c
index e215af9..5299f21 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -683,7 +683,28 @@  static void set_hflags_for_handler (CPUMIPSState *env)
 static inline void set_badinstr_registers(CPUMIPSState *env)
 {
     if (env->hflags & MIPS_HFLAG_M16) {
-        /* TODO: add BadInstr support for microMIPS */
+        uint32_t instr;
+        if (!(env->insn_flags & ISA_NANOMIPS32)) {
+            /* TODO: add BadInstr support for pre-nanoMIPS */
+             return;
+        }
+        if (env->CP0_Config3 & (1 << CP0C3_BI)) {
+            instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
+            if ((env->insn_flags & ISA_NANOMIPS32) &&
+                ((instr & 0x10000000) == 0)) {
+                instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
+            }
+            env->CP0_BadInstr = instr;
+        }
+        if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
+            (env->hflags & MIPS_HFLAG_BMASK)) {
+            if (!(env->hflags & MIPS_HFLAG_B16)) {
+                env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
+            } else {
+                env->CP0_BadInstrP =
+                    (cpu_lduw_code(env, env->active_tc.PC - 2)) << 16;
+            }
+        }
         return;
     }
     if (env->CP0_Config3 & (1 << CP0C3_BI)) {