diff mbox series

[v3,18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions

Message ID 1532004912-13899-19-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Add emulation of various nanoMIPS load and store instructions.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 271 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 271 insertions(+)

Comments

Richard Henderson July 20, 2018, 4:59 a.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> +        case NM_ADDIUGP_B:
> +            gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
> +            break;

Use gen_op_addr_add, since behaves_like('DADDIU[GP.B]').

>      case NM_P_LS_U12:
> +    {
> +        uint32_t u = extract32(ctx->opcode, 0, 12);
> +        switch ((ctx->opcode >> 12) & 0x0f) {
> +        case NM_P_PREFU12:
> +            if (rt == 31) {
> +                /* SYNCI */
> +                /* Break the TB to be able to sync copied instructions
> +                   immediately */
> +                ctx->base.is_jmp = DISAS_STOP;

I'll note for future cleanup that while this matches all of the other instances
of SYNCI in target/mips/, this is not actually required.

QEMU supports self-modifying code without any barriers or breaks whatsoever.
(Becuase, of course, i386 as a guest requires this.)


r~
Aleksandar Markovic July 25, 2018, 3:46 p.m. UTC | #2 
Hello, Richard. Sorry for bothering you. One more question.

> On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> > +        case NM_ADDIUGP_B:
> > +            gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
> > +            break;
>
> Use gen_op_addr_add, since behaves_like('DADDIU[GP.B]').

Did you perhaps mean an implementation similar to this would be appropriate:

case NM_ADDIUGP_B:
    if (rt != 0) { 
        uint32_t offset = extract32(ctx->opcode, 0, 18); 
        if (offset == 0) { 
            gen_load_gpr(cpu_gpr[rt], 28); 
        } else { 
            TCGv t0; 
            t0 = tcg_temp_new(); 
            tcg_gen_movi_tl(t0, offset); 
            gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0); 
            tcg_temp_free(t0); 
        } 
    }
    break;

(this is like NM_ADDIUGP_W implementation)

Aleksandar M.
Richard Henderson July 25, 2018, 7:18 p.m. UTC | #3 
On 07/25/2018 08:46 AM, Aleksandar Markovic wrote:
> Hello, Richard. Sorry for bothering you. One more question.
> 
>> On 07/19/2018 05:54 AM, Stefan Markovic wrote:
>>> +        case NM_ADDIUGP_B:
>>> +            gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
>>> +            break;
>>
>> Use gen_op_addr_add, since behaves_like('DADDIU[GP.B]').
> 
> Did you perhaps mean an implementation similar to this would be appropriate:
> 
> case NM_ADDIUGP_B:
>     if (rt != 0) { 
>         uint32_t offset = extract32(ctx->opcode, 0, 18); 
>         if (offset == 0) { 
>             gen_load_gpr(cpu_gpr[rt], 28); 
>         } else { 
>             TCGv t0; 
>             t0 = tcg_temp_new(); 
>             tcg_gen_movi_tl(t0, offset); 
>             gen_op_addr_add(ctx, cpu_gpr[rt], cpu_gpr[28], t0); 
>             tcg_temp_free(t0); 
>         } 
>     }
>     break;
> 
> (this is like NM_ADDIUGP_W implementation)

I have suggested in the past (during v1 or v2 review?) creating

static void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
                             target_long ofs)
{
    tcg_gen_addi_tl(ret, base, ofs);
#ifdef TARGET_MIPS64
    if (ctx->hflags & MIPS_HFLAG_AWRAP) {
        tcg_gen_ext32s_i64(ret, ret);
    }
#endif
}

so that

(1) You need not locally maintain the tcg temporary for offset
    at each such instance,
(2) The special case for offset == 0 is handled automatically
    within tcg_gen_addi_tl.
(3) You do not forget, as you just did here, that the extension
    for AWRAP must happen even for offset == 0.


r~
Peter Maydell July 25, 2018, 7:32 p.m. UTC | #4 
On 20 July 2018 at 05:59, Richard Henderson
<richard.henderson@linaro.org> wrote:
> On 07/19/2018 05:54 AM, Stefan Markovic wrote:
>> +                /* SYNCI */
>> +                /* Break the TB to be able to sync copied instructions
>> +                   immediately */
>> +                ctx->base.is_jmp = DISAS_STOP;
>
> I'll note for future cleanup that while this matches all of the other instances
> of SYNCI in target/mips/, this is not actually required.
>
> QEMU supports self-modifying code without any barriers or breaks whatsoever.
> (Becuase, of course, i386 as a guest requires this.)

This is true, but only if the target/ code defines
TARGET_HAS_PRECISE_SMC (which at the moment only target/i386
does), which enables some complicated code that spots
when the current TB is being modified. Most of our
other targets only support self-modifying code which
has some kind of barrier insn, and break the TB at
the barrier. (Compare Arm's handling of "isb", though
there there is also an architectural requirement to take
any pending interrupts at the barrier; I don't know if
MIPS has any similar interrupt related semantics for
their SYNCI.)

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 29d1f19..5dc6582 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17668,10 +17668,281 @@  static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
         }
         break;
     case NM_P_GP_BH:
+    {
+        uint32_t u = extract32(ctx->opcode, 0, 18);
+        switch ((ctx->opcode >> 18) & 0x7) {
+        case NM_LBGP:
+            gen_ld(ctx, OPC_LB, rt, 28, u);
+            break;
+        case NM_SBGP:
+            gen_st(ctx, OPC_SB, rt, 28, u);
+            break;
+        case NM_LBUGP:
+            gen_ld(ctx, OPC_LBU, rt, 28, u);
+            break;
+        case NM_ADDIUGP_B:
+            gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
+            break;
+        case NM_P_GP_LH:
+            u &= ~1;
+            switch (ctx->opcode & 1) {
+            case NM_LHGP:
+                gen_ld(ctx, OPC_LH, rt, 28, u);
+                break;
+            case NM_LHUGP:
+                gen_ld(ctx, OPC_LHU, rt, 28, u);
+                break;
+            }
+            break;
+        case NM_P_GP_SH:
+            u &= ~1;
+            switch (ctx->opcode & 1) {
+            case NM_SHGP:
+                gen_st(ctx, OPC_SH, rt, 28, u);
+                break;
+            default:
+                generate_exception_end(ctx, EXCP_RI);
+                break;
+            }
+            break;
+        case NM_P_GP_CP1:
+            u &= ~0x3;
+            switch ((ctx->opcode & 0x3)) {
+            case NM_LWC1GP:
+                gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
+                break;
+            case NM_LDC1GP:
+                gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
+                break;
+            case NM_SWC1GP:
+                gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
+                break;
+            case NM_SDC1GP:
+                gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
+                break;
+            }
+            break;
+        default:
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+    }
         break;
     case NM_P_LS_U12:
+    {
+        uint32_t u = extract32(ctx->opcode, 0, 12);
+        switch ((ctx->opcode >> 12) & 0x0f) {
+        case NM_P_PREFU12:
+            if (rt == 31) {
+                /* SYNCI */
+                /* Break the TB to be able to sync copied instructions
+                   immediately */
+                ctx->base.is_jmp = DISAS_STOP;
+            } else {
+                /* PREF */
+                /* Treat as NOP. */
+            }
+            break;
+        case NM_LB:
+            gen_ld(ctx, OPC_LB, rt, rs, u);
+            break;
+        case NM_LH:
+            gen_ld(ctx, OPC_LH, rt, rs, u);
+            break;
+        case NM_LW:
+            gen_ld(ctx, OPC_LW, rt, rs, u);
+            break;
+        case NM_LBU:
+            gen_ld(ctx, OPC_LBU, rt, rs, u);
+            break;
+        case NM_LHU:
+            gen_ld(ctx, OPC_LHU, rt, rs, u);
+            break;
+        case NM_SB:
+            gen_st(ctx, OPC_SB, rt, rs, u);
+            break;
+        case NM_SH:
+            gen_st(ctx, OPC_SH, rt, rs, u);
+            break;
+        case NM_SW:
+            gen_st(ctx, OPC_SW, rt, rs, u);
+            break;
+        case NM_LWC1:
+            gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
+            break;
+        case NM_LDC1:
+            gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
+            break;
+        case NM_SWC1:
+            gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
+            break;
+        case NM_SDC1:
+            gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
+            break;
+        default:
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+    }
         break;
     case NM_P_LS_S9:
+    {
+        int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
+                    extract32(ctx->opcode, 0, 8);
+        switch ((ctx->opcode >> 8) & 0x07) {
+        case NM_P_LS_S0:
+            switch ((ctx->opcode >> 11) & 0x0f) {
+            case NM_LBS9:
+                gen_ld(ctx, OPC_LB, rt, rs, s);
+                break;
+            case NM_LHS9:
+                gen_ld(ctx, OPC_LH, rt, rs, s);
+                break;
+            case NM_LWS9:
+                gen_ld(ctx, OPC_LW, rt, rs, s);
+                break;
+            case NM_LBUS9:
+                gen_ld(ctx, OPC_LBU, rt, rs, s);
+                break;
+            case NM_LHUS9:
+                gen_ld(ctx, OPC_LHU, rt, rs, s);
+                break;
+            case NM_SBS9:
+                gen_st(ctx, OPC_SB, rt, rs, s);
+                break;
+            case NM_SHS9:
+                gen_st(ctx, OPC_SH, rt, rs, s);
+                break;
+            case NM_SWS9:
+                gen_st(ctx, OPC_SW, rt, rs, s);
+                break;
+            case NM_LWC1S9:
+                gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, s);
+                break;
+            case NM_LDC1S9:
+                gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, s);
+                break;
+            case NM_SWC1S9:
+                gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, s);
+                break;
+            case NM_SDC1S9:
+                gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, s);
+                break;
+            case NM_P_PREFS9:
+                if (rt == 31) {
+                    /* SYNCI */
+                    /* Break the TB to be able to sync copied instructions
+                       immediately */
+                    ctx->base.is_jmp = DISAS_STOP;
+                } else {
+                    /* PREF */
+                    /* Treat as NOP. */
+                }
+                break;
+            default:
+                generate_exception_end(ctx, EXCP_RI);
+                break;
+            }
+            break;
+        case NM_P_LS_S1:
+            switch ((ctx->opcode >> 11) & 0x0f) {
+            case NM_UALH:
+            case NM_UASH:
+            {
+                TCGv t0 = tcg_temp_new();
+                TCGv t1 = tcg_temp_new();
+
+                gen_base_offset_addr(ctx, t0, rs, s);
+
+                switch ((ctx->opcode >> 11) & 0x0f) {
+                case NM_UALH:
+                    tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+                                       MO_UNALN);
+                    gen_store_gpr(t0, rt);
+                    break;
+                case NM_UASH:
+                    gen_load_gpr(t1, rt);
+                    tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+                                       MO_UNALN);
+                    break;
+                }
+                tcg_temp_free(t0);
+                tcg_temp_free(t1);
+            }
+                break;
+            case NM_P_LL:
+                switch (ctx->opcode & 0x03) {
+                case NM_LL:
+                    gen_ld(ctx, OPC_LL, rt, rs, s);
+                    break;
+                case NM_LLWP:
+                    break;
+                }
+                break;
+            case NM_P_SC:
+                switch (ctx->opcode & 0x03) {
+                case NM_SC:
+                    gen_st_cond(ctx, OPC_SC, rt, rs, s);
+                    break;
+                case NM_SCWP:
+                    break;
+                }
+                break;
+            case NM_CACHE:
+                check_cp0_enabled(ctx);
+                if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
+                    gen_cache_operation(ctx, rt, rs, s);
+                }
+                break;
+            }
+            break;
+        case NM_P_LS_WM:
+        case NM_P_LS_UAWM:
+        {
+            int32_t offset = sextract32(ctx->opcode, 15, 1) << 8 |
+                            extract32(ctx->opcode, 0, 8);
+            int count = extract32(ctx->opcode, 12, 3);
+            int counter = 0;
+            TCGv va = tcg_temp_new();
+            TCGv t1 = tcg_temp_new();
+            TCGMemOp memop = ((ctx->opcode >> 8) & 0x07) == NM_P_LS_UAWM ?
+                            MO_UNALN : 0;
+
+            count = (count == 0) ? 8 : count;
+            while (counter != count) {
+                int this_rt = ((rt + counter) & 0x1f) | (rt & 0x10);
+                int32_t this_offset = offset + (counter << 2);
+
+                gen_base_offset_addr(ctx, va, rs, this_offset);
+
+                switch (extract32(ctx->opcode, 11, 1)) {
+                case NM_LWM:
+                    tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
+                                       memop | MO_TESL);
+                    gen_store_gpr(t1, this_rt);
+                    if ((this_rt == rs) &&
+                        (counter != (count - 1))) {
+                        /* UNPREDICTABLE */
+                    }
+                    break;
+                case NM_SWM:
+                    this_rt = (rt == 0) ? 0 : this_rt;
+                    gen_load_gpr(t1, this_rt);
+                    tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
+                                       memop | MO_TEUL);
+                    break;
+                }
+                counter++;
+            }
+            tcg_temp_free(va);
+            tcg_temp_free(t1);
+        }
+            break;
+        default:
+            generate_exception_end(ctx, EXCP_RI);
+            break;
+        }
+    }
         break;
     case NM_MOVE_BALC:
         break;