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[v3,27/40] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS

Message ID 1532004912-13899-28-git-send-email-stefan.markovic@rt-rk.com
State New
Headers show
Series Add nanoMIPS support to QEMU | expand

Commit Message

Stefan Markovic July 19, 2018, 12:54 p.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Config3.ISAOnExc is read only in nanoMIPS.

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
---
 target/mips/op_helper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Richard Henderson July 23, 2018, 4:48 p.m. UTC | #1 
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> -    if (env->insn_flags & ASE_MICROMIPS) {
> +    if ((env->insn_flags & ASE_MICROMIPS) &&
> +        !(env->insn_flags & ISA_NANOMIPS32)) {

Why is ASE_MICROMIPS ever set at the same time as ISA_NANOMIPS?
This change ought not be necessary, AFAIU.


r~
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Patch

diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index cb83b6d..5e10286 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1730,7 +1730,8 @@  void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
 
 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
 {
-    if (env->insn_flags & ASE_MICROMIPS) {
+    if ((env->insn_flags & ASE_MICROMIPS) &&
+        !(env->insn_flags & ISA_NANOMIPS32)) {
         env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
                            (arg1 & (1 << CP0C3_ISA_ON_EXC));
     }