From patchwork Wed Jul 18 19:48:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 945884 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="nJm0NNuG"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41W75C3tz0z9s4r for ; Thu, 19 Jul 2018 05:49:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730511AbeGRU21 (ORCPT ); Wed, 18 Jul 2018 16:28:27 -0400 Received: from mail.kernel.org ([198.145.29.99]:35722 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730470AbeGRU21 (ORCPT ); Wed, 18 Jul 2018 16:28:27 -0400 Received: from localhost.localdomain (xdsl-188-155-58-14.adslplus.ch [188.155.58.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6EF6720854; Wed, 18 Jul 2018 19:49:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1531943343; bh=Fq1gXMX9zvkLkTTQHgvkpo75y+eNfXxD45yODz2Z32o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJm0NNuGVnvytAaEZjC8kC0PDSE9R7A1YI6+cDM4OUThd+WxCqg+oSaLaHeBE26Ue v303DDMbMSW6bBmx0Ts9lugm2p2cdZfHBrwFD4b8J0taSC30pbClUX1WZtFLhF6ulu gSwz+LsVpQdF3i/AtUQwn+WhbY/1KM+9tRg4ynXg= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Marcel Ziswiler , Stefan Agner , Lucas Stach , Thomas Gleixner , Greg Kroah-Hartman , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Philippe Ombredanne , Krzysztof Kozlowski Subject: [PATCH 3/3] ARM: tegra: tegra20: Fix mixed tabs-spaces indentation Date: Wed, 18 Jul 2018 21:48:24 +0200 Message-Id: <20180718194824.3704-3-krzk@kernel.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180718194824.3704-1-krzk@kernel.org> References: <20180718194824.3704-1-krzk@kernel.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Fix indentation and alignment when spaces were used instead of tabs. This fixes checkpatch errors like: ERROR: code indent should use tabs where possible #306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306: +^I^I <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;$ Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +- arch/arm/boot/dts/tegra20-paz00.dts | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index e7b9ab09908a..fa1af2dc276c 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -541,7 +541,7 @@ sound { compatible = "nvidia,tegra-audio-wm9712-colibri_t20", - "nvidia,tegra-audio-wm9712"; + "nvidia,tegra-audio-wm9712"; nvidia,model = "Colibri T20 AC97 Audio"; nvidia,audio-routing = diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ef245291924f..7d8aef6ebd3a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -303,7 +303,7 @@ request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; resets = <&tegra_car 67>; reset-names = "i2c"; @@ -599,8 +599,8 @@ GPIO_ACTIVE_HIGH>; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; };