From patchwork Wed Jul 18 07:12:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksij Rempel X-Patchwork-Id: 945527 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41VpJY0s1Dz9s89 for ; Wed, 18 Jul 2018 17:13:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726982AbeGRHtV (ORCPT ); Wed, 18 Jul 2018 03:49:21 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:49767 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726067AbeGRHtV (ORCPT ); Wed, 18 Jul 2018 03:49:21 -0400 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1ffgdp-00068T-2t; Wed, 18 Jul 2018 09:12:53 +0200 Received: from ore by dude.hi.pengutronix.de with local (Exim 4.91) (envelope-from ) id 1ffgdo-0002KA-EX; Wed, 18 Jul 2018 09:12:52 +0200 From: Oleksij Rempel To: Shawn Guo , Fabio Estevam , Rob Herring , Mark Rutland , "A.s. Dong" Cc: Oleksij Rempel , kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dl-linux-imx Subject: [PATCH v4 2/4] dt-bindings: arm: fsl: rework mu doc Date: Wed, 18 Jul 2018 09:12:49 +0200 Message-Id: <20180718071251.8857-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180718071251.8857-1-o.rempel@pengutronix.de> References: <20180718071251.8857-1-o.rempel@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org - Remove software specific description. MU has many use cases limited only by imagination. So remove this confusing part. - Add all currently known SoCs with MU - Make sure this documentation covers not only Firmware specific use case. Parameters for generic configurations should be described as well. Signed-off-by: Oleksij Rempel --- .../devicetree/bindings/mailbox/fsl,mu.txt | 32 +++++++++---------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index 90e4905dfc69..9d5e6ee61e22 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -1,28 +1,26 @@ NXP i.MX Messaging Unit (MU) -------------------------------------------------------------------- -The Messaging Unit module enables two processors within the SoC to -communicate and coordinate by passing messages (e.g. data, status -and control) through the MU interface. The MU also provides the ability -for one processor to signal the other processor using interrupts. - -Because the MU manages the messaging between processors, the MU uses -different clocks (from each side of the different peripheral buses). -Therefore, the MU must synchronize the accesses from one side to the -other. The MU accomplishes synchronization using two sets of matching -registers (Processor A-facing, Processor B-facing). - -Messaging Unit Device Node: -============================= - Required properties: ------------------- -- compatible : should be "fsl,-mu", the supported chips include - imx8qxp, imx8qm. +- compatible : should be "fsl,-mu", the supported chips include: + fsl,imx6sx-mu - i.MX 6SoloX + fsl,imx7d-mu - i.MX 7Dual + fsl,imx7s-mu - i.MX 7Solo + fsl,imx7ulp-mu - i.MX 7ULP + fsl,imx8qm-mu - i.MX 8QM + fsl,imx8qxp-mu - i.MX 8QXP - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. -- #mbox-cells: Must be 0. Number of cells in a mailbox +- #mbox-cells: Must be: + 0 - for single channel mode. i.MX8* SCU protocol specific. + 1 - for multichannel (generic) mode. + +Optional properties: +------------------- +- clocks : phandle to the input clock. +- fsl,mu-side-b : Should be set for side B MU. Examples: --------