| Message ID | 20180717153135.25925-1-mr.nuke.me@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | PCI/AER: Do not clear AER bits if we don't own AER | expand |
On 7/17/2018 8:31 AM, Alexandru Gagniuc wrote: > + if (pcie_aer_get_firmware_first(dev)) > + return -EIO; Can you move this to closer to the caller pci_aer_init()?
On 07/17/2018 10:41 AM, Sinan Kaya wrote: > > On 7/17/2018 8:31 AM, Alexandru Gagniuc wrote: >> + if (pcie_aer_get_firmware_first(dev)) >> + return -EIO; > > Can you move this to closer to the caller pci_aer_init()? I could move it there. although pci_cleanup_aer_error_status_regs() is called directly from pci_restore_state. Of course, aer_cap should be zero in this case, and we'd still bail out. I find the intent clearer if we check it here rather than having to do the mental parsing of the state of aer_cap. Alex
On 7/19/2018 8:55 AM, Alex G. wrote: > I find the intent clearer if we check it here rather than having to do > the mental parsing of the state of aer_cap. I don't feel too strong about my comment to be honest. This was a style/maintenance comment. It feels like we are putting pcie_aer_get_firmware_first() into core functions unnecessarily after your change. I understand the need for your change. I'm asking if it is the right place or not. pcie_aer_get_firmware_first() should be called from either the init or probe function so that the rest of the AER functions do not get called from any other context. If someone adds another AER function, we might need to add another pcie_aer_get_firmware_first() check there. So, we have unnecessary code duplication.
On 07/19/2018 11:58 AM, Sinan Kaya wrote: > > On 7/19/2018 8:55 AM, Alex G. wrote: >> I find the intent clearer if we check it here rather than having to do >> the mental parsing of the state of aer_cap. > > I don't feel too strong about my comment to be honest. This was a > style/maintenance comment. > > It feels like we are putting pcie_aer_get_firmware_first() into core > functions unnecessarily after your change. I understand the need for > your change. I'm asking if it is the right place or not. > > pcie_aer_get_firmware_first() should be called from either the init or > probe function so that the rest of the AER functions do not get called > from any other context. > > If someone adds another AER function, we might need to add another > pcie_aer_get_firmware_first() check there. So, we have unnecessary code > duplication. We could move the aer_cap and get_ffs() check into one function that we end up calling all over the place. I understand your concern about code duplication, and I agree with it. I don't think that at this point it's that big of a deal, although we might need to guard every aer_() call. So moving all the checks in a pcie_aer_is_kernel_first() makes sense. Alex
On Tue, Jul 17, 2018 at 10:31:23AM -0500, Alexandru Gagniuc wrote: > When we don't own AER, we shouldn't touch the AER error bits. This > happens unconditionally on device probe(). Clearing AER bits > willy-nilly might cause firmware to miss errors. Instead > these bits should get cleared by FFS, or via ACPI _HPX method. > > This race is mostly of theoretical significance, as it is not easy to > reasonably demonstrate it in testing. > > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> > --- > drivers/pci/pcie/aer.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index a2e88386af28..18037a2a8231 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -383,6 +383,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) > if (!pci_is_pcie(dev)) > return -ENODEV; > > + if (pcie_aer_get_firmware_first(dev)) > + return -EIO; I like this patch. Do we need the same thing in the following places that also clear AER status bits or write AER control bits? enable_ecrc_checking() disable_ecrc_checking() pci_cleanup_aer_uncorrect_error_status() pci_aer_clear_fatal_status() > pos = dev->aer_cap; > if (!pos) > return -EIO; > -- > 2.14.3 >
On 08/09/2018 09:16 AM, Bjorn Helgaas wrote: > On Tue, Jul 17, 2018 at 10:31:23AM -0500, Alexandru Gagniuc wrote: >> When we don't own AER, we shouldn't touch the AER error bits. This >> happens unconditionally on device probe(). Clearing AER bits >> willy-nilly might cause firmware to miss errors. Instead >> these bits should get cleared by FFS, or via ACPI _HPX method. >> >> This race is mostly of theoretical significance, as it is not easy to >> reasonably demonstrate it in testing. >> >> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> >> --- >> drivers/pci/pcie/aer.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c >> index a2e88386af28..18037a2a8231 100644 >> --- a/drivers/pci/pcie/aer.c >> +++ b/drivers/pci/pcie/aer.c >> @@ -383,6 +383,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) >> if (!pci_is_pcie(dev)) >> return -ENODEV; >> >> + if (pcie_aer_get_firmware_first(dev)) >> + return -EIO; > > I like this patch. > > Do we need the same thing in the following places that also clear AER > status bits or write AER control bits? In theory, every exported function would guard for this. I think the idea a long long time ago was that the check happens during initialization, and the others are not hit. > enable_ecrc_checking() > disable_ecrc_checking() I don't immediately see how this would affect FFS, but the bits are part of the AER capability structure. According to the FFS model, those would be owned by FW, and we'd have to avoid touching them. > pci_cleanup_aer_uncorrect_error_status() This probably should be guarded. It's only called from a few specific drivers, so the impact is not as high as being called from the core. > pci_aer_clear_fatal_status() This is only called when doing fatal_recovery, right? For practical considerations this is not an issue today. The ACPI error handling code currently crashes when it encounters any fatal error, so we wouldn't hit this in the FFS case. If the ACPI code pulls its thinking appendage out of the other end of the digestive tract, then we could be hitting this in the future. For correctness, guarding makes sense. The PCIe standards contact I usually talk to about these PCIe subtleties is currently on vacation. The number one issue was a FFS corner case with OS clearing bits on probe. The other functions you mention are a corner case of a corner case. The big fish is pci_cleanup_aer_error_status_regs() on probe(), and it would be nice to have that resolved. I'll sync up with Austin when he gets back to see about the other functions though I suspect we'll end up fixing them as well. Alex >> pos = dev->aer_cap; >> if (!pos) >> return -EIO; >> -- >> 2.14.3 >> >
On Thu, Aug 09, 2018 at 04:46:32PM +0000, Alex_Gagniuc@Dellteam.com wrote: > On 08/09/2018 09:16 AM, Bjorn Helgaas wrote: > > On Tue, Jul 17, 2018 at 10:31:23AM -0500, Alexandru Gagniuc wrote: > >> When we don't own AER, we shouldn't touch the AER error bits. This > >> happens unconditionally on device probe(). Clearing AER bits > >> willy-nilly might cause firmware to miss errors. Instead > >> these bits should get cleared by FFS, or via ACPI _HPX method. > >> > >> This race is mostly of theoretical significance, as it is not easy to > >> reasonably demonstrate it in testing. > >> > >> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> > >> --- > >> drivers/pci/pcie/aer.c | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > >> index a2e88386af28..18037a2a8231 100644 > >> --- a/drivers/pci/pcie/aer.c > >> +++ b/drivers/pci/pcie/aer.c > >> @@ -383,6 +383,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) > >> if (!pci_is_pcie(dev)) > >> return -ENODEV; > >> > >> + if (pcie_aer_get_firmware_first(dev)) > >> + return -EIO; > > > > I like this patch. > > > > Do we need the same thing in the following places that also clear AER > > status bits or write AER control bits? > > In theory, every exported function would guard for this. I think the > idea a long long time ago was that the check happens during > initialization, and the others are not hit. > > > enable_ecrc_checking() > > disable_ecrc_checking() > > I don't immediately see how this would affect FFS, but the bits are part > of the AER capability structure. According to the FFS model, those would > be owned by FW, and we'd have to avoid touching them. Per ACPI v6.2, sec 18.3.2.4, the HEST may contain entries for Root Ports that contain the FIRMWARE_FIRST flag as well as values the OS is supposed to write to several AER capability registers. It looks like we currently ignore everything except the FIRMWARE_FIRST and GLOBAL flags (ACPI_HEST_FIRMWARE_FIRST and ACPI_HEST_GLOBAL in Linux). That seems like a pretty major screwup and more than I want to fix right now. > > pci_cleanup_aer_uncorrect_error_status() > > This probably should be guarded. It's only called from a few specific > drivers, so the impact is not as high as being called from the core. > > > pci_aer_clear_fatal_status() > > This is only called when doing fatal_recovery, right? True. It takes a lot of analysis to convince oneself that this is not used in the firmware-first path, so I think we should add a guard there. > For practical considerations this is not an issue today. The ACPI error > handling code currently crashes when it encounters any fatal error, so > we wouldn't hit this in the FFS case. I wasn't aware the firmware-first path was *that* broken. Are there problem reports for this? Is this a regression? > The PCIe standards contact I usually talk to about these PCIe subtleties > is currently on vacation. The number one issue was a FFS corner case > with OS clearing bits on probe. The other functions you mention are a > corner case of a corner case. The big fish is > pci_cleanup_aer_error_status_regs() on probe(), and it would be nice to > have that resolved. > > I'll sync up with Austin when he gets back to see about the other > functions though I suspect we'll end up fixing them as well. I'd like to fix all the obvious cases at once (excluding the ECRC stuff). What do you think about the following patch? commit 15ed68dcc26864c849a12a36db4d4771bad7991f Author: Alexandru Gagniuc <mr.nuke.me@gmail.com> Date: Tue Jul 17 10:31:23 2018 -0500 PCI/AER: Don't clear AER bits if error handling is Firmware-First If the platform requests Firmware-First error handling, firmware is responsible for reading and clearing AER status bits. If OSPM also clears them, we may miss errors. See ACPI v6.2, sec 18.3.2.5 and 18.4. This race is mostly of theoretical significance, as it is not easy to reasonably demonstrate it in testing. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [bhelgaas: add similar guards to pci_cleanup_aer_uncorrect_error_status() and pci_aer_clear_fatal_status()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index c6cc855bfa22..4e823ae051a7 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -397,6 +397,9 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) if (!pos) return -EIO; + if (pcie_aer_get_firmware_first(dev)) + return -EIO; + /* Clear status bits for ERR_NONFATAL errors only */ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); @@ -417,6 +420,9 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (!pos) return; + if (pcie_aer_get_firmware_first(dev)) + return; + /* Clear status bits for ERR_FATAL errors only */ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); @@ -438,6 +444,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) if (!pos) return -EIO; + if (pcie_aer_get_firmware_first(dev)) + return -EIO; + port_type = pci_pcie_type(dev); if (port_type == PCI_EXP_TYPE_ROOT_PORT) { pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);
On 08/09/2018 01:29 PM, Bjorn Helgaas wrote: > On Thu, Aug 09, 2018 at 04:46:32PM +0000, Alex_Gagniuc@Dellteam.com wrote: >> On 08/09/2018 09:16 AM, Bjorn Helgaas wrote: (snip_ >>> enable_ecrc_checking() >>> disable_ecrc_checking() >> >> I don't immediately see how this would affect FFS, but the bits are part >> of the AER capability structure. According to the FFS model, those would >> be owned by FW, and we'd have to avoid touching them. > > Per ACPI v6.2, sec 18.3.2.4, the HEST may contain entries for Root > Ports that contain the FIRMWARE_FIRST flag as well as values the OS is > supposed to write to several AER capability registers. It looks like > we currently ignore everything except the FIRMWARE_FIRST and GLOBAL > flags (ACPI_HEST_FIRMWARE_FIRST and ACPI_HEST_GLOBAL in Linux). > > That seems like a pretty major screwup and more than I want to fix > right now. The logic is not very clear, but I think it goes like this: For GLOBAL and FFS, disable native AER everywhere. When !GLOBAL and FFS, then only disable native AER for the root port described by the HEST entry. aer_acpi_firmware_first() doesn't care about context. Though check aer_set_firmware_first(), where we pass a pci_device as a context. The FFS implementations I've seen have one HEST entry, with GLOBAL and FFS. I have yet to see more fine-grained control of root ports. I suspect that if we had this finer control from HEST, we'd honor it. I do eventually want to get a test BIOS with different HEST entries, and make sure things work as intended. Though BIOS team is overloaded with other requests. >>> pci_cleanup_aer_uncorrect_error_status() >> >> This probably should be guarded. It's only called from a few specific >> drivers, so the impact is not as high as being called from the core. >> >>> pci_aer_clear_fatal_status() >> >> This is only called when doing fatal_recovery, right? > > True. It takes a lot of analysis to convince oneself that this is not > used in the firmware-first path, so I think we should add a guard > there. I agree. GHES has a header severity and a severity field for each section. All BIOSes I've seen do fatal/fatal, though a BIOS that would report correctable/fatal, would bypass the apei code and take us here. >> For practical considerations this is not an issue today. The ACPI error >> handling code currently crashes when it encounters any fatal error, so >> we wouldn't hit this in the FFS case. > > I wasn't aware the firmware-first path was *that* broken. Are there > problem reports for this? Is this a regression? It's been like this since, I believe, 3.10, and probably much earlier. All reports that I have seen of linux crashing on surprise hot-plug have been caused by the panic() call in the apei code. Dell BIOSes do an extreme amount of work to determine when it's safe to _not_ report errors to the OS, since all known OSes crash on this path. Fun fact: there's even dedicated hardware to accomplish the above. >> The PCIe standards contact I usually talk to about these PCIe subtleties >> is currently on vacation. The number one issue was a FFS corner case >> with OS clearing bits on probe. The other functions you mention are a >> corner case of a corner case. The big fish is >> pci_cleanup_aer_error_status_regs() on probe(), and it would be nice to >> have that resolved. >> >> I'll sync up with Austin when he gets back to see about the other >> functions though I suspect we'll end up fixing them as well. > > I'd like to fix all the obvious cases at once (excluding the ECRC > stuff). What do you think about the following patch? That looks very sensible to me. Thank you for updating it :). I'm pulling in the changes right now to run some quick tests, and I don't expect any trouble. Alex > commit 15ed68dcc26864c849a12a36db4d4771bad7991f > Author: Alexandru Gagniuc <mr.nuke.me@gmail.com> > Date: Tue Jul 17 10:31:23 2018 -0500 > > PCI/AER: Don't clear AER bits if error handling is Firmware-First > > If the platform requests Firmware-First error handling, firmware is > responsible for reading and clearing AER status bits. If OSPM also clears > them, we may miss errors. See ACPI v6.2, sec 18.3.2.5 and 18.4. > > This race is mostly of theoretical significance, as it is not easy to > reasonably demonstrate it in testing. > > Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> > [bhelgaas: add similar guards to pci_cleanup_aer_uncorrect_error_status() > and pci_aer_clear_fatal_status()] > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index c6cc855bfa22..4e823ae051a7 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -397,6 +397,9 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) > if (!pos) > return -EIO; > > + if (pcie_aer_get_firmware_first(dev)) > + return -EIO; > + > /* Clear status bits for ERR_NONFATAL errors only */ > pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); > pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); > @@ -417,6 +420,9 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) > if (!pos) > return; > > + if (pcie_aer_get_firmware_first(dev)) > + return; > + > /* Clear status bits for ERR_FATAL errors only */ > pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); > pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev); > @@ -438,6 +444,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) > if (!pos) > return -EIO; > > + if (pcie_aer_get_firmware_first(dev)) > + return -EIO; > + > port_type = pci_pcie_type(dev); > if (port_type == PCI_EXP_TYPE_ROOT_PORT) { > pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status); >
On Thu, Aug 09, 2018 at 02:00:23PM -0500, Alex G. wrote: > On 08/09/2018 01:29 PM, Bjorn Helgaas wrote: > > On Thu, Aug 09, 2018 at 04:46:32PM +0000, Alex_Gagniuc@Dellteam.com wrote: > > > On 08/09/2018 09:16 AM, Bjorn Helgaas wrote: > (snip_ > > > > enable_ecrc_checking() > > > > disable_ecrc_checking() > > > > > > I don't immediately see how this would affect FFS, but the bits are part > > > of the AER capability structure. According to the FFS model, those would > > > be owned by FW, and we'd have to avoid touching them. > > > > Per ACPI v6.2, sec 18.3.2.4, the HEST may contain entries for Root > > Ports that contain the FIRMWARE_FIRST flag as well as values the OS is > > supposed to write to several AER capability registers. It looks like > > we currently ignore everything except the FIRMWARE_FIRST and GLOBAL > > flags (ACPI_HEST_FIRMWARE_FIRST and ACPI_HEST_GLOBAL in Linux). > > > > That seems like a pretty major screwup and more than I want to fix > > right now. > > The logic is not very clear, but I think it goes like this: > For GLOBAL and FFS, disable native AER everywhere. > When !GLOBAL and FFS, then only disable native AER for the root port > described by the HEST entry. I agree the code is convoluted, but that sounds right to me. What I meant is that we ignore the values the HEST entry tells us we're supposed to write to Device Control and the AER Uncorrectable Error Mask, Uncorrectable Error Severity, Correctable Error Mask, and AER Capabilities and Control. > > > For practical considerations this is not an issue today. The ACPI error > > > handling code currently crashes when it encounters any fatal error, so > > > we wouldn't hit this in the FFS case. > > > > I wasn't aware the firmware-first path was *that* broken. Are there > > problem reports for this? Is this a regression? > > It's been like this since, I believe, 3.10, and probably much earlier. All > reports that I have seen of linux crashing on surprise hot-plug have been > caused by the panic() call in the apei code. Dell BIOSes do an extreme > amount of work to determine when it's safe to _not_ report errors to the OS, > since all known OSes crash on this path. Oh, is this the __ghes_panic() path? If so, I'm going to turn away and plead ignorance unless the PCI core is doing something wrong that eventually results in that panic.
On 08/09/2018 02:18 PM, Bjorn Helgaas wrote: > On Thu, Aug 09, 2018 at 02:00:23PM -0500, Alex G. wrote: >> On 08/09/2018 01:29 PM, Bjorn Helgaas wrote: >>> On Thu, Aug 09, 2018 at 04:46:32PM +0000, Alex_Gagniuc@Dellteam.com wrote: >>>> On 08/09/2018 09:16 AM, Bjorn Helgaas wrote: >> (snip_ >>>>> enable_ecrc_checking() >>>>> disable_ecrc_checking() >>>> >>>> I don't immediately see how this would affect FFS, but the bits are part >>>> of the AER capability structure. According to the FFS model, those would >>>> be owned by FW, and we'd have to avoid touching them. >>> >>> Per ACPI v6.2, sec 18.3.2.4, the HEST may contain entries for Root >>> Ports that contain the FIRMWARE_FIRST flag as well as values the OS is >>> supposed to write to several AER capability registers. It looks like >>> we currently ignore everything except the FIRMWARE_FIRST and GLOBAL >>> flags (ACPI_HEST_FIRMWARE_FIRST and ACPI_HEST_GLOBAL in Linux). >>> >>> That seems like a pretty major screwup and more than I want to fix >>> right now. >> >> The logic is not very clear, but I think it goes like this: >> For GLOBAL and FFS, disable native AER everywhere. >> When !GLOBAL and FFS, then only disable native AER for the root port >> described by the HEST entry. > > I agree the code is convoluted, but that sounds right to me. > > What I meant is that we ignore the values the HEST entry tells us > we're supposed to write to Device Control and the AER Uncorrectable > Error Mask, Uncorrectable Error Severity, Correctable Error Mask, and > AER Capabilities and Control. Wait, what? _HPX has the same information. This is madness! Since root ports are not hot-swappable, the BIOS normally programs those registers. Even if linux doesn't apply said masks, the programming BIOS did should be sufficient to have *cough* correct *cough* behavior. >>>> For practical considerations this is not an issue today. The ACPI error >>>> handling code currently crashes when it encounters any fatal error, so >>>> we wouldn't hit this in the FFS case. >>> >>> I wasn't aware the firmware-first path was *that* broken. Are there >>> problem reports for this? Is this a regression? >> >> It's been like this since, I believe, 3.10, and probably much earlier. All >> reports that I have seen of linux crashing on surprise hot-plug have been >> caused by the panic() call in the apei code. Dell BIOSes do an extreme >> amount of work to determine when it's safe to _not_ report errors to the OS, >> since all known OSes crash on this path. > > Oh, is this the __ghes_panic() path? If so, I'm going to turn away > and plead ignorance unless the PCI core is doing something wrong that > eventually results in that panic. I agree, and I'll quote you on that! Alex
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index a2e88386af28..18037a2a8231 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -383,6 +383,9 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) if (!pci_is_pcie(dev)) return -ENODEV; + if (pcie_aer_get_firmware_first(dev)) + return -EIO; + pos = dev->aer_cap; if (!pos) return -EIO;
When we don't own AER, we shouldn't touch the AER error bits. This happens unconditionally on device probe(). Clearing AER bits willy-nilly might cause firmware to miss errors. Instead these bits should get cleared by FFS, or via ACPI _HPX method. This race is mostly of theoretical significance, as it is not easy to reasonably demonstrate it in testing. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> --- drivers/pci/pcie/aer.c | 3 +++ 1 file changed, 3 insertions(+)