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[211.20.114.70]) by smtp.gmail.com with ESMTPSA id f6-v6sm578647pgp.13.2018.07.17.00.28.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Jul 2018 00:28:12 -0700 (PDT) From: Ryan Chen To: openbmc@lists.ozlabs.org Subject: [PATCH linux dev-4.17 2/7] clk: Aspeed: Add sdhci reset and clock Date: Tue, 17 Jul 2018 15:26:13 +0800 Message-Id: <1531812378-14316-3-git-send-email-ryanchen.aspeed@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531812378-14316-1-git-send-email-ryanchen.aspeed@gmail.com> References: <1531812378-14316-1-git-send-email-ryanchen.aspeed@gmail.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan_chen@aspeedtech.com, andrew@aj.id.au, Ryan Chen Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" 1.Add Aspeed sdhci reset for SCU04 bit 16 2.Aspeed sdhci have two clock one is for controller clock, another is for SD card clock. so when enable sdhci need enable both. v0->V2 Use aspeed_resets[ASPEED_RESET_SDHCI] replace the maginc number 16 move aspeed_resets in front of aspeed_clk_enable function Signed-off-by: Ryan Chen --- drivers/clk/clk-aspeed.c | 44 ++++++++++++++++++-------------- include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 9e55743..f399da2 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -20,6 +20,7 @@ #define ASPEED_RESET_CTRL 0x04 #define ASPEED_CLK_SELECTION 0x08 +#define ASPEED_SDIO_CLK_EN BIT(15) #define ASPEED_CLK_STOP_CTRL 0x0c #define ASPEED_MPLL_PARAM 0x20 #define ASPEED_HPLL_PARAM 0x24 @@ -208,6 +209,25 @@ static const struct aspeed_clk_soc_data ast2400_data = { .calc_pll = aspeed_ast2400_calc_pll, }; +static const u8 aspeed_resets[] = { + /* SCU04 resets */ + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PECI] = 10, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, + [ASPEED_RESET_SDHCI] = 16, + /* + * SCUD4 resets start at an offset to separate them from + * the SCU04 resets. + */ + [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, +}; + static int aspeed_clk_is_enabled(struct clk_hw *hw) { struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); @@ -260,6 +280,11 @@ static int aspeed_clk_enable(struct clk_hw *hw) enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); + /* sd ext clk */ + if (gate->reset_idx == aspeed_resets[ASPEED_RESET_SDHCI]) { + regmap_update_bits(gate->map, ASPEED_CLK_SELECTION, ASPEED_SDIO_CLK_EN, ASPEED_SDIO_CLK_EN); + } + if (gate->reset_idx >= 0) { /* A delay of 10ms is specified by the ASPEED docs */ mdelay(10); @@ -306,25 +331,6 @@ struct aspeed_reset { #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) -static const u8 aspeed_resets[] = { - /* SCU04 resets */ - [ASPEED_RESET_XDMA] = 25, - [ASPEED_RESET_MCTP] = 24, - [ASPEED_RESET_ADC] = 23, - [ASPEED_RESET_JTAG_MASTER] = 22, - [ASPEED_RESET_MIC] = 18, - [ASPEED_RESET_PWM] = 9, - [ASPEED_RESET_PECI] = 10, - [ASPEED_RESET_I2C] = 2, - [ASPEED_RESET_AHB] = 1, - - /* - * SCUD4 resets start at an offset to separate them from - * the SCU04 resets. - */ - [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, -}; - static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4476184..088553f 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -50,5 +50,5 @@ #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 - +#define ASPEED_RESET_SDHCI 10 #endif