diff mbox series

[U-Boot,4/6] stm32mp1: clk: update Ethernet clock gating

Message ID 1531730506-18633-4-git-send-email-patrick.delaunay@st.com
State Accepted
Commit 04365530c00c200167056bb5053f5eabdd3fbcc9
Delegated to: Tom Rini
Headers show
Series [U-Boot,1/6] stm32mp1: clk: define RCC_PLLNCFGR2_SHIFT macro | expand

Commit Message

Patrick DELAUNAY July 16, 2018, 8:41 a.m. UTC 
Alignment with kernel clock driver

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
---

 drivers/clk/clk_stm32mp1.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Tom Rini July 20, 2018, 10:36 p.m. UTC | #1 
On Mon, Jul 16, 2018 at 10:41:44AM +0200, Patrick Delaunay wrote:

> Alignment with kernel clock driver
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 6202ebe..0641dfa 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -542,10 +542,9 @@  static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
 
-	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _UNKNOWN_SEL),
+	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK, _ETH_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
-	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 10, ETHMAC_K, _ETH_SEL),
 	STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),