From patchwork Fri May 6 17:32:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Berger X-Patchwork-Id: 94412 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2FD871007D1 for ; Sat, 7 May 2011 03:33:55 +1000 (EST) Received: from localhost ([::1]:56297 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIOuW-0006lp-1C for incoming@patchwork.ozlabs.org; Fri, 06 May 2011 13:33:52 -0400 Received: from eggs.gnu.org ([140.186.70.92]:43841) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIOtz-0006hS-DL for qemu-devel@nongnu.org; Fri, 06 May 2011 13:33:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QIOtx-0003s4-ES for qemu-devel@nongnu.org; Fri, 06 May 2011 13:33:19 -0400 Received: from e37.co.us.ibm.com ([32.97.110.158]:53844) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIOtx-0003rn-9F for qemu-devel@nongnu.org; Fri, 06 May 2011 13:33:17 -0400 Received: from d03relay03.boulder.ibm.com (d03relay03.boulder.ibm.com [9.17.195.228]) by e37.co.us.ibm.com (8.14.4/8.13.1) with ESMTP id p46HUK8s001575 for ; Fri, 6 May 2011 11:30:20 -0600 Received: from d03av02.boulder.ibm.com (d03av02.boulder.ibm.com [9.17.195.168]) by d03relay03.boulder.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p46HX65j105242 for ; Fri, 6 May 2011 11:33:08 -0600 Received: from d03av02.boulder.ibm.com (loopback [127.0.0.1]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p46BWKcd004431 for ; Fri, 6 May 2011 05:32:21 -0600 Received: from localhost.localdomain (d941e-10.watson.ibm.com [9.59.241.154]) by d03av02.boulder.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id p46BWJcT004363 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 6 May 2011 05:32:20 -0600 Received: from localhost.localdomain (d941e-10 [127.0.0.1]) by localhost.localdomain (8.14.4/8.14.3) with ESMTP id p46HWkcP001363; Fri, 6 May 2011 13:32:46 -0400 Received: (from root@localhost) by localhost.localdomain (8.14.4/8.14.4/Submit) id p46HWkrV001362; Fri, 6 May 2011 13:32:46 -0400 Message-Id: <20110506173246.173039002@linux.vnet.ibm.com> User-Agent: quilt/0.48-1 Date: Fri, 06 May 2011 13:32:29 -0400 From: Stefan Berger To: stefanb@linux.vnet.ibm.com, qemu-devel@nongnu.org References: <20110506173224.278066589@linux.vnet.ibm.com> Content-Disposition: inline; filename=qemu_tpm_tis_debugreg.diff X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 32.97.110.158 Cc: andreas.niederl@iaik.tugraz.at, serge@hallyn.com Subject: [Qemu-devel] [PATCH V4 05/10] Add a debug register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch uses the possibility to add a vendor-specific register and adds a debug register useful for dumping the TIS's internal state. This register is only active in a debug build (#define DEBUG_TIS). v3: - all output goes to stderr Signed-off-by: Stefan Berger --- hw/tpm_tis.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) Index: qemu-git/hw/tpm_tis.c =================================================================== --- qemu-git.orig/hw/tpm_tis.c +++ qemu-git/hw/tpm_tis.c @@ -42,6 +42,8 @@ #define TIS_REG_DID_VID 0xf00 #define TIS_REG_RID 0xf04 +/* vendor-specific registers */ +#define TIS_REG_DEBUG 0xf90 #define STS_VALID (1 << 7) #define STS_COMMAND_READY (1 << 6) @@ -356,6 +358,66 @@ static uint32_t tis_data_read(TPMState * } +#ifdef DEBUG_TIS +static void tis_dump_state(void *opaque, target_phys_addr_t addr) +{ + static const unsigned regs[] = { + TIS_REG_ACCESS, + TIS_REG_INT_ENABLE, + TIS_REG_INT_VECTOR, + TIS_REG_INT_STATUS, + TIS_REG_INTF_CAPABILITY, + TIS_REG_STS, + TIS_REG_DID_VID, + TIS_REG_RID, + 0xfff}; + int idx; + uint8_t locty = tis_locality_from_addr(addr); + target_phys_addr_t base = addr & ~0xfff; + TPMState *s = opaque; + + fprintf(stderr, + "tpm_tis: active locality : %d\n" + "tpm_tis: state of locality %d : %d\n" + "tpm_tis: register dump:\n", + s->active_locty, + locty, s->loc[locty].state); + + for (idx = 0; regs[idx] != 0xfff; idx++) { + fprintf(stderr, "tpm_tis: 0x%04x : 0x%08x\n", regs[idx], + tis_mem_readl(opaque, base + regs[idx])); + } + + fprintf(stderr, + "tpm_tis: read offset : %d\n" + "tpm_tis: result buffer : ", + s->loc[locty].r_offset); + for (idx = 0; + idx < tis_get_size_from_buffer(&s->loc[locty].r_buffer); + idx++) { + fprintf(stderr, "%c%02x%s", + s->loc[locty].r_offset == idx ? '>' : ' ', + s->loc[locty].r_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + fprintf(stderr, + "\n" + "tpm_tis: write offset : %d\n" + "tpm_tis: request buffer: ", + s->loc[locty].w_offset); + for (idx = 0; + idx < tis_get_size_from_buffer(&s->loc[locty].w_buffer); + idx++) { + fprintf(stderr, "%c%02x%s", + s->loc[locty].w_offset == idx ? '>' : ' ', + s->loc[locty].w_buffer.buffer[idx], + ((idx & 0xf) == 0xf) ? "\ntpm_tis: " : ""); + } + fprintf(stderr,"\n"); +} +#endif + + /* * Read a register of the TIS interface * See specs pages 33-63 for description of the registers @@ -431,6 +493,11 @@ static uint32_t tis_mem_readl(void *opaq case TIS_REG_RID: val = TPM_RID; break; +#ifdef DEBUG_TIS + case TIS_REG_DEBUG: + tis_dump_state(opaque, addr); + break; +#endif } qemu_mutex_unlock(&s->state_lock);