[1/2] riscv: add support for RISC-V Instruction Set

Message ID 6de3f8a7-5e83-2f5a-d09c-f44504d602a4@aries-embedded.de
State Superseded
Headers show
Series
  • support for RISC-V architecture
Related show

Commit Message

Anton Kuzmin July 14, 2018, 7:12 a.m.

Patch

Signed-off-by: Anton Kuzmin <ak@aries-embedded.de>
---
 arch/Config.in       | 13 +++++++++
 arch/Config.in.riscv | 68 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)
 create mode 100644 arch/Config.in.riscv

diff --git a/arch/Config.in b/arch/Config.in
index 7d1aeb2174..b50a19f6e3 100644
--- a/arch/Config.in
+++ b/arch/Config.in
@@ -198,6 +198,15 @@  config BR2_powerpc64le
 	  http://www.power.org/
 	  http://en.wikipedia.org/wiki/Powerpc
 
+config BR2_riscv
+	bool "RISC-V"
+	select BR2_ARCH_HAS_MMU_OPTIONAL
+	help
+	  RISC-V is an open, free Instruction Set Architecture created
+	  by the UC Berkeley Architecture Research group and supported
+	  and promoted by RISC-V Foundation.
+	  https://riscv.org/
+
 config BR2_sh
 	bool "SuperH"
 	select BR2_ARCH_HAS_MMU_OPTIONAL
@@ -423,6 +432,10 @@  if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
 source "arch/Config.in.powerpc"
 endif
 
+if BR2_riscv
+source "arch/Config.in.riscv"
+endif
+
 if BR2_sh
 source "arch/Config.in.sh"
 endif
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
new file mode 100644
index 0000000000..31c25a92c2
--- /dev/null
+++ b/arch/Config.in.riscv
@@ -0,0 +1,68 @@ 
+# RISC-V CPU Base ISA and Extensions
+
+choice
+	prompt "Base RISC-V Integer ISA"
+	default BR2_rv64i
+	help
+	  Base RISC-V ISA variant to use
+
+#config BR2_rv32i
+#	bool "32-bit: RV32I"
+#	select BR2_RISCV_CPU_RV32I
+#	select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+
+config BR2_rv64i
+	bool "64-bit: RV64I"
+	select BR2_RISCV_CPU_RV64I
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+
+endchoice
+
+comment "Standard RISC-V Extensions"
+#	Default choices form Generic extension set: MFDA
+
+config BR2_riscv_m
+	bool "Multiply and Divide"
+	default y
+config BR2_riscv_f
+	bool "Signle-Precision Floating Point"
+	default y
+config BR2_riscv_d
+	bool "Double-Precision Floating Point"
+	default y
+config BR2_riscv_a
+	bool "Atomic Instructions"
+	default y
+config BR2_riscv_c
+	bool "Compressed Instructions"
+config BR2_riscv_v
+	bool "Vector Instructions"
+
+comment "Future Optional RISC-V Extensions"
+
+config BR2_riscv_b
+	bool "Bit Manipulation"
+config BR2_riscv_e
+	bool "Embedded (reduced number of registers)"
+config BR2_riscv_h
+	bool "Privileged Extension for Hypervisor Support"
+config BR2_riscv_j
+	bool "Extension for Dynamically Translated Languages"
+config BR2_riscv_l
+	bool "Decimal Floating Point"
+config BR2_riscv_n
+	bool "User-Level Interrupts"
+config BR2_riscv_p
+	bool "Packed-SIMD Instructions"
+config BR2_riscv_q
+	bool "Quad-Precision Floating Point"
+
+config BR2_ARCH
+	default "riscv32"	if BR2_rv32i
+	default "riscv64"	if BR2_rv64i
+
+config BR2_ENDIAN
+	default "LITTLE"
+
+config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
+	default y
-- 
2.18.0