From patchwork Fri May 6 12:00:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 94368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4C3C4B6EFF for ; Fri, 6 May 2011 22:01:24 +1000 (EST) Received: from localhost ([::1]:38016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJii-0005fi-NY for incoming@patchwork.ozlabs.org; Fri, 06 May 2011 08:01:20 -0400 Received: from eggs.gnu.org ([140.186.70.92]:35442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJi7-0005Xy-QN for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QIJi5-0003rN-3l for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:43 -0400 Received: from cantor.suse.de ([195.135.220.2]:58825 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJi4-0003q9-Fh for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:40 -0400 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 2680494109; Fri, 6 May 2011 14:00:38 +0200 (CEST) From: Alexander Graf To: QEMU-devel Developers Date: Fri, 6 May 2011 14:00:37 +0200 Message-Id: <1304683237-26177-8-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1304683237-26177-1-git-send-email-agraf@suse.de> References: <1304683237-26177-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.2 Cc: Scott Wood , "Edgar E. Iglesias" , Liu Yu Subject: [Qemu-devel] [PATCH 7/7] PPC: Qdev'ify e500 pci X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The e500 PCI controller isn't qdev'ified yet. This leads to severe issues when running with -drive. To be able to use a virtio disk with an e500 VM, let's convert the PCI controller over to qdev. Signed-off-by: Alexander Graf --- v2 -> v3: - rebase to current code base - fix endian issue - use sysbus helpers v3 -> v4: - drop base_addr --- hw/ppce500_pci.c | 111 +++++++++++++++++++++++++++++++++++------------------- 1 files changed, 72 insertions(+), 39 deletions(-) diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 83a20e4..f3db0a7 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -73,11 +73,10 @@ struct pci_inbound { }; struct PPCE500PCIState { + PCIHostState pci_state; struct pci_outbound pob[PPCE500_PCI_NR_POBS]; struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; uint32_t gasket_time; - PCIHostState pci_state; - PCIDevice *pci_dev; }; typedef struct PPCE500PCIState PPCE500PCIState; @@ -250,7 +249,6 @@ static const VMStateDescription vmstate_ppce500_pci = { .minimum_version_id = 1, .minimum_version_id_old = 1, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState), VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, vmstate_pci_outbound, struct pci_outbound), VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, @@ -262,58 +260,93 @@ static const VMStateDescription vmstate_ppce500_pci = { PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) { - PPCE500PCIState *controller; + DeviceState *dev; + PCIBus *b; + PCIHostState *h; + PPCE500PCIState *s; PCIDevice *d; - int index; static int ppce500_pci_id; + SysBusDevice *sb; + + dev = qdev_create(NULL, "e500-pcihost"); + sb = sysbus_from_qdev(dev); + h = FROM_SYSBUS(PCIHostState, sb); + s = DO_UPCAST(PPCE500PCIState, pci_state, h); + + b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq, + mpc85xx_pci_map_irq, pci_irqs, PCI_DEVFN(0x11, 0), 4); - controller = qemu_mallocz(sizeof(PPCE500PCIState)); + s->pci_state.bus = b; + qdev_init_nofail(dev); + d = pci_create_simple(b, 0, "e500-host-bridge"); - controller->pci_state.bus = pci_register_bus(NULL, "pci", - mpc85xx_pci_set_irq, - mpc85xx_pci_map_irq, - pci_irqs, PCI_DEVFN(0x11, 0), - 4); - d = pci_register_device(controller->pci_state.bus, - "host bridge", sizeof(PCIDevice), - 0, NULL, NULL); + sysbus_mmio_map(sb, 0, registers + PCIE500_CFGADDR); + sysbus_mmio_map(sb, 1, registers + PCIE500_CFGDATA); + sysbus_mmio_map(sb, 2, registers + PCIE500_REG_BASE); - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE); - pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E); - pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC); + /* XXX load/save code not tested. */ + vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci, s); + + return b; +} + +static int e500_pcihost_initfn(SysBusDevice *dev) +{ + PCIHostState *h; + PPCE500PCIState *s; + /* XXX qdev var */ + int index; - controller->pci_dev = d; + h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); + s = DO_UPCAST(PPCE500PCIState, pci_state, h); /* CFGADDR */ - index = pci_host_conf_register_mmio(&controller->pci_state, - DEVICE_BIG_ENDIAN); + index = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN); if (index < 0) - goto free; - cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index); + return -1; + sysbus_init_mmio(dev, 4, index); /* CFGDATA */ - index = pci_host_data_register_mmio(&controller->pci_state, - DEVICE_BIG_ENDIAN); + index = pci_host_data_register_mmio(&s->pci_state, DEVICE_LITTLE_ENDIAN); if (index < 0) - goto free; - cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index); + return -1; + sysbus_init_mmio(dev, 4, index); index = cpu_register_io_memory(e500_pci_reg_read, - e500_pci_reg_write, controller, - DEVICE_NATIVE_ENDIAN); + e500_pci_reg_write, s, DEVICE_BIG_ENDIAN); if (index < 0) - goto free; - cpu_register_physical_memory(registers + PCIE500_REG_BASE, - PCIE500_REG_SIZE, index); + return -1; + sysbus_init_mmio(dev, PCIE500_REG_SIZE, index); + return 0; +} - /* XXX load/save code not tested. */ - vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci, - controller); +static int e500_host_bridge_initfn(PCIDevice *dev) +{ + pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE); + pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E); + pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC); + + return 0; +} - return controller->pci_state.bus; +static PCIDeviceInfo e500_host_bridge_info = { + .qdev.name = "e500-host-bridge", + .qdev.desc = "Host bridge", + .qdev.size = sizeof(PCIDevice), + .qdev.no_user = 1, + .init = e500_host_bridge_initfn, +}; -free: - printf("%s error\n", __func__); - qemu_free(controller); - return NULL; +static SysBusDeviceInfo e500_pcihost_info = { + .init = e500_pcihost_initfn, + .qdev.name = "e500-pcihost", + .qdev.size = sizeof(PPCE500PCIState), + .qdev.no_user = 1, +}; + +static void e500_pci_register(void) +{ + sysbus_register_withprop(&e500_pcihost_info); + pci_qdev_register(&e500_host_bridge_info); } +device_init(e500_pci_register);