From patchwork Fri May 6 12:00:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 94366 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 92A44B6F07 for ; Fri, 6 May 2011 22:01:17 +1000 (EST) Received: from localhost ([::1]:37856 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJia-0005Yt-5d for incoming@patchwork.ozlabs.org; Fri, 06 May 2011 08:01:12 -0400 Received: from eggs.gnu.org ([140.186.70.92]:35405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJi6-0005XU-DK for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QIJi3-0003pu-Su for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:41 -0400 Received: from cantor.suse.de ([195.135.220.2]:58816 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QIJi3-0003oe-Gz for qemu-devel@nongnu.org; Fri, 06 May 2011 08:00:39 -0400 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 181BC93F19; Fri, 6 May 2011 14:00:38 +0200 (CEST) From: Alexander Graf To: QEMU-devel Developers Date: Fri, 6 May 2011 14:00:33 +0200 Message-Id: <1304683237-26177-4-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1304683237-26177-1-git-send-email-agraf@suse.de> References: <1304683237-26177-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.2 Cc: Scott Wood , "Edgar E. Iglesias" , Liu Yu Subject: [Qemu-devel] [PATCH 3/7] PPC: Add GS MSR definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The BookE specification defines MSR bit 28 as Guest State. Add it to the list of MSR macros. Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 303f8ce..c6b2255 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -420,6 +420,7 @@ struct ppc_slb_t { #define MSR_CM 31 /* Computation mode for BookE hflags */ #define MSR_ICM 30 /* Interrupt computation mode for BookE */ #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ +#define MSR_GS 28 /* guest state for BookE */ #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ #define MSR_VR 25 /* altivec available x hflags */ #define MSR_SPE 25 /* SPE enable for BookE x hflags */ @@ -457,6 +458,7 @@ struct ppc_slb_t { #define msr_cm ((env->msr >> MSR_CM) & 1) #define msr_icm ((env->msr >> MSR_ICM) & 1) #define msr_thv ((env->msr >> MSR_THV) & 1) +#define msr_gs ((env->msr >> MSR_GS) & 1) #define msr_ucle ((env->msr >> MSR_UCLE) & 1) #define msr_vr ((env->msr >> MSR_VR) & 1) #define msr_spe ((env->msr >> MSR_SPE) & 1)