From patchwork Fri Jul 13 11:32:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "David R. Piegdon" X-Patchwork-Id: 943440 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=p23q.org Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=p23q.org header.i=@p23q.org header.b="F8e5PuhW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41RrJh0lyHz9s0n for ; Fri, 13 Jul 2018 21:32:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727608AbeGMLrG (ORCPT ); Fri, 13 Jul 2018 07:47:06 -0400 Received: from mail.gnuzifer.de ([78.46.242.17]:52709 "EHLO mail.gnuzifer.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727582AbeGMLrG (ORCPT ); Fri, 13 Jul 2018 07:47:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=p23q.org; s=20170531; h=Content-Type:MIME-Version:Date:Message-ID:To:Subject:From; bh=PK9fTEDOioUFP14MTuAGkwhjF6tjWa6xetL5mcZAtNE=; b=F8e5PuhWNflG6N2ua0uuNRcJLIW6AZ38Vv9ykVrO3Yqn/XBg3J1S6/pFMxp3XcZkqpcX0D7pCcVrRkFu2rIyvJqMYSHPyiA1hdjj3fa3HmiKx7+ehKUsfhfp1SDwQSXfcSAWGDHeAbf1a060R4MdCg1kXIcVRe9OuJ7GvlRuvcEF2p4uNg4Bwx98KYV5+eQsW/zQ/rhtLrN2F4ZFPuyWzl8rlp0AMjmQoyRx7uWJXd6tJMdxNz7fARiIww8WhPVxGtWlNJwm1LQsFS6T9AJBtB7N4tq33JCBXyoMTllFnHUlbtXN7MCCN0+MjxD2wuwp5sPw7gmcYjkf+Wz60XxzXNcYF5ck2OqwrL4EmMGBha3cfOTjprHL2puVzIeSZ/NVH1vPD2B1RxHpEC25UD5sVaeiWOZWuwfUSjzkSyNHarjjNIxLfTEu6zIcx1b3s7K92nNPFCpDEschZohPL8a+fosJ5+Z58QhQ0yhHzjNmoFd7GS99X8DN9MXM3hRFbGUWmPo7lxJ3IfA/DvTcR40Fn0P1m9/KHBfqZQFQWrg/2H3CTmYqsKHH78LUCK26n8tAN6tlavfcCACta+2XNqe81HL51fczivhlpMDN78njOcz8QxpXwUgde/ua1HUtpK6/qz1gs86bKd2p7/Wc4AHz+KC8+Fq7X1eknyse5cgFKew=; Received: from authenticated user by mail.gnuzifer.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2) (envelope-from ) id 1fdwJc-00054q-8x for linux-tegra@vger.kernel.org; Fri, 13 Jul 2018 13:32:48 +0200 From: "David R. Piegdon" Subject: [PATCH] serial8250 on tegra hsuart: recover from spurious interrupts due to tegra2 silicon bug To: linux-tegra@vger.kernel.org Message-ID: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org> Date: Fri, 13 Jul 2018 11:32:42 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 Content-Language: en-GB Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Hi, a while back I sent a few mails regarding spurious interrupts in the UARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for it instead of the hsuart driver. After going down a pretty deep debugging/testing hole, I think I found a patch that fixes the issue. So far testing in a reboot-cycle suggests that the error frequency dropped from >3% of all reboots to at least <0.05% of all reboots. Tests continue to run over the weekend. The patch below already is a second iteration; the first did not reset the MCR or contain the lines below '// clear interrupts'. This resulted in no more spurious interrupts, but in a few % of spurious interrupts that were recovered the UART block did not receive any characters any more. So further resetting was required to fully reacquire operational state of the UART block. I'd love any comments/suggestions on this! Cheers, David diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index e8819aa20415..1d76eebefd4e 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -140,6 +140,38 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id) "serial8250: too much work for irq%d\n", irq); break; } + +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + if (!handled && (port->type == PORT_TEGRA)) { + /* + * Fix Tegra 2 CPU silicon bug where sometimes + * "TX holding register empty" interrupts result in a + * bad (metastable?) state in Tegras HSUART IP core. + * Only way to recover seems to be to reset all + * interrupts as well as the TX queue and the MCR. + * But we don't want to loose any outgoing characters, + * so only do it if the RX and TX queues are empty. + */ + unsigned char lsr = port->serial_in(port, UART_LSR); + const unsigned char fifo_empty_mask = + (UART_LSR_TEMT | UART_LSR_THRE); + if (((lsr & (UART_LSR_DR | fifo_empty_mask)) == + fifo_empty_mask)) { + port->serial_out(port, UART_IER, 0); + port->serial_out(port, UART_MCR, 0); + serial8250_clear_and_reinit_fifos(up); + port->serial_out(port, UART_MCR, up->mcr); + port->serial_out(port, UART_IER, up->ier); + // clear interrupts + serial_port_in(port, UART_LSR); + serial_port_in(port, UART_RX); + serial_port_in(port, UART_IIR); + serial_port_in(port, UART_MSR); + up->lsr_saved_flags = 0; + up->msr_saved_flags = 0; + } + } +#endif } while (l != end); spin_unlock(&i->lock);