[RESEND] mmc: tegra: enable ddr_signaling for MMC_TIMING_MMC_DDR52

Message ID 20180712173837.2921-1-tszucs@protonmail.ch
State New
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Series
  • [RESEND] mmc: tegra: enable ddr_signaling for MMC_TIMING_MMC_DDR52
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Commit Message

Tamás Szűcs July 12, 2018, 5:38 p.m.
This fixes sampling errors with eMMC modules using DDR52 when host capabilities
via setting NVQUIRK_ENABLE_DDR50 and NVQUIRK_ENABLE_SDHCI_SPEC_300 are enabled.

Signed-off-by: Tamás Szűcs <tszucs@protonmail.ch>
---
 drivers/mmc/host/sdhci-tegra.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 970d38f68939..a3bfaa7067c8 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -228,7 +228,7 @@  static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
 
-	if (timing == MMC_TIMING_UHS_DDR50)
+	if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
 		tegra_host->ddr_signaling = true;
 
 	sdhci_set_uhs_signaling(host, timing);