From patchwork Thu Jul 12 11:52:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 942961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41RDpc3YZcz9s2M for ; Thu, 12 Jul 2018 21:53:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726723AbeGLMCW (ORCPT ); Thu, 12 Jul 2018 08:02:22 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15511 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbeGLMCW (ORCPT ); Thu, 12 Jul 2018 08:02:22 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 12 Jul 2018 04:52:24 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 12 Jul 2018 04:53:09 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 12 Jul 2018 04:53:09 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 12 Jul 2018 11:53:09 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 12 Jul 2018 11:53:09 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Thu, 12 Jul 2018 11:53:09 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 12 Jul 2018 04:53:08 -0700 From: Aapo Vienamo To: Peter De Schrijver CC: Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , , , , Aapo Vienamo Subject: [PATCH v6 1/4] clk: tegra: Fix includes required by fence_udelay() Date: Thu, 12 Jul 2018 14:52:59 +0300 Message-ID: <1531396382-5579-2-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531396382-5579-1-git-send-email-avienamo@nvidia.com> References: <1531396382-5579-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver Acked-by: Jon Hunter --- drivers/clk/tegra/clk.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index e1f8846..e3b9c22 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -19,6 +19,7 @@ #include #include +#include /** * struct tegra_clk_sync_source - external clock source from codec