From patchwork Thu Jul 12 10:26:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 942894 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-94200-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="lSfa8dfb"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41RBwk4kXhz9ryt for ; Thu, 12 Jul 2018 20:28:22 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type; q=dns; s=default; b=OpSbs zF7yKGfQzz3jHgOBEArmcmV9sdVgnQiOz+AIHTYZNeBedjZ/sras12Mz0K63x0Xr 8oDIgToD74YtRdcCPdGpwEtvd+V/ytV/qn2+HZrelTMe6G7aEoRdxHHNsVvNr0PZ 7Qmdn03dZ9FnBn1MeDZbq0mMNfwaCFfJcyBpkg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type; s=default; bh=NCpRCNB6BVo t3NX6fRsxYfcl4GY=; b=lSfa8dfbM02ZIq179SkIHoc1IeFfhXnCi2DZQaABVfM B2Vs7v4GLWvqznDETpV1viYFQwhlQcoRTsY5zd3gzxj2f3HDHIaHC2V9i6B729Iu 532afKU7266x1f8Bq6EyZ3N+/fdifcv5mnUJ3NUthk7PwmRRm4kLSH//HM4CRTRs = Received: (qmail 81089 invoked by alias); 12 Jul 2018 10:27:56 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 80928 invoked by uid 89); 12 Jul 2018 10:27:54 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=33021 X-HELO: ATCSQR.andestech.com From: Zong Li To: , , , , , CC: , Zong Li Subject: [PATCH 9/9] Add 32 bit RISC-V to build-many-glibcs.py Date: Thu, 12 Jul 2018 18:26:25 +0800 Message-ID: <4aee5401c3e8163c166d85df6820122b30dc18dc.1531384754.git.zong@andestech.com> In-Reply-To: References: MIME-Version: 1.0 X-DNSRBL: X-MAIL: ATCSQR.andestech.com w6CASn75016793 Support building three variant of 32 bit RISC-V glibc. --- scripts/build-many-glibcs.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py index 601718d..4bbb730 100755 --- a/scripts/build-many-glibcs.py +++ b/scripts/build-many-glibcs.py @@ -330,6 +330,21 @@ class Context(object): variant='e500v1', gcc_cfg=['--disable-multilib', '--enable-secureplt', '--enable-obsolete']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imac-ilp32', + gcc_cfg=['--with-arch=rv32imac', '--with-abi=ilp32', + '--disable-multilib']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imafdc-ilp32', + gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32', + '--disable-multilib']) + self.add_config(arch='riscv32', + os_name='linux-gnu', + variant='rv32imafdc-ilp32d', + gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d', + '--disable-multilib']) self.add_config(arch='riscv64', os_name='linux-gnu', variant='rv64imac-lp64',