| Message ID | 1531394014-12620-2-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Accepted |
| Commit | 8c9f247a1a2031b200c04f297d5b9ae1353d9d90 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot] arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only | expand |
On 07/12/2018 01:13 PM, Ley Foon Tan wrote: > MCR instruction only available in ARM 32-bit. So, compile MCR instruction > when ARM 32-bit is enabled. > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > arch/arm/mach-socfpga/board.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c > index cb6530f..26d84be 100644 > --- a/arch/arm/mach-socfpga/board.c > +++ b/arch/arm/mach-socfpga/board.c > @@ -19,6 +19,7 @@ > DECLARE_GLOBAL_DATA_PTR; > > void s_init(void) { > +#ifndef CONFIG_ARM64 > /* > * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. > * This is optional on CycloneV / ArriaV. > @@ -29,6 +30,7 @@ void s_init(void) { > "isb\n" > "dsb\n" > ::"r"(0x0)); > +#endif > } > > /* > Applied, thanks
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index cb6530f..26d84be 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; void s_init(void) { +#ifndef CONFIG_ARM64 /* * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled. * This is optional on CycloneV / ArriaV. @@ -29,6 +30,7 @@ void s_init(void) { "isb\n" "dsb\n" ::"r"(0x0)); +#endif } /*
MCR instruction only available in ARM 32-bit. So, compile MCR instruction when ARM 32-bit is enabled. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- arch/arm/mach-socfpga/board.c | 2 ++ 1 file changed, 2 insertions(+)