[U-Boot] mtd: add spi flash id s25fl128l

Message ID 48967cc2.AMMAAA9BrmcAAAAAAAAAAALjdEIAAAAA0lkAAAAAAAkLgwBbRbPt@mailjet.com
State Changes Requested
Delegated to: Jagannadha Sutradharudu Teki
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Series
  • [U-Boot] mtd: add spi flash id s25fl128l
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Commit Message

Clément Laigle July 11, 2018, 7:38 a.m.
From: Clement Laigle <c.laigle@catie.fr>

Add support for SPANSION s25fl128l 256k and 64k

Signed-off-by: Clément Laigle <c.laigle@catie.fr>
---
 drivers/mtd/spi/spi_flash_ids.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Jagan Teki July 16, 2018, 8:52 a.m. | #1
On Wed, Jul 11, 2018 at 1:08 PM, Clément Laigle <c.laigle@catie.fr> wrote:
> From: Clement Laigle <c.laigle@catie.fr>
>
> Add support for SPANSION s25fl128l 256k and 64k
>
> Signed-off-by: Clément Laigle <c.laigle@catie.fr>
> ---
>  drivers/mtd/spi/spi_flash_ids.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
> index 9212373dae..f7e9e92955 100644
> --- a/drivers/mtd/spi/spi_flash_ids.c
> +++ b/drivers/mtd/spi/spi_flash_ids.c
> @@ -107,6 +107,8 @@ const struct spi_flash_info spi_flash_ids[] = {
>         {"s25fl064p",      INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL | WR_QPP) },
>         {"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024,    64, RD_FULL | WR_QPP) },
>         {"s25fl128s_64k",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | WR_QPP) },
> +       {"s25fl128l_256k", INFO(0x016018, 0x0, 256 * 1024,    64, RD_FULL | WR_QPP) },
> +       {"s25fl128l_64k",  INFO(0x016018, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },

256 vs 64 have change in EXT_ID, update the same otherwise it will
detect 256k even if the chip is 64k

Patch

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 9212373dae..f7e9e92955 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -107,6 +107,8 @@  const struct spi_flash_info spi_flash_ids[] = {
 	{"s25fl064p",	   INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL | WR_QPP) },
 	{"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024,    64, RD_FULL | WR_QPP) },
 	{"s25fl128s_64k",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | WR_QPP) },
+	{"s25fl128l_256k", INFO(0x016018, 0x0, 256 * 1024,    64, RD_FULL | WR_QPP) },
+	{"s25fl128l_64k",  INFO(0x016018, 0x0,  64 * 1024,   256, RD_FULL | WR_QPP) },
 	{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | WR_QPP) },
 	{"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | WR_QPP | SECT_4K) },
 	{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | WR_QPP) },