| Message ID | 1531213054-63327-2-git-send-email-jingqi.liu@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | x86/cpu: Enable a few new cpu features | expand |
On Tue, Jul 10, 2018 at 04:57:32PM +0800, Jingqi Liu wrote: > UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions. > > UMONITOR arms address monitoring hardware using an address. A store > to an address within the specified address range triggers the > monitoring hardware to wake up the processor waiting in umwait. > > UMWAIT instructs the processor to enter an implementation-dependent > optimized state while monitoring a range of addresses. The optimized > state may be either a light-weight power/performance optimized state > or an improved power/performance optimized state. > > TPAUSE instructs the processor to enter an implementation-dependent > optimized state c0.1 or c0.2 state and wake up when time-stamp counter > reaches specified timeout. > > The bit definition: > CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG > > The release document ref below link: > https://software.intel.com/sites/default/files/managed/c5/15/\ > architecture-instruction-set-extensions-programming-reference.pdf > > Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Is it really OK to expose these features to the guest without "-overcommit cpu-pm=on"? Don't we need code to migrate IA32_UMWAIT_CONTROL? (I don't see code to handle writes to IA32_UMWAIT_CONTROL on the KVM patches, either.)
> -----Original Message----- > From: Eduardo Habkost [mailto:ehabkost@redhat.com] > Sent: Tuesday, August 7, 2018 6:03 AM > To: Liu, Jingqi <jingqi.liu@intel.com> > Cc: pbonzini@redhat.com; rth@twiddle.net; Wang, Wei W > <wei.w.wang@intel.com>; qemu-devel@nongnu.org; Michael S. Tsirkin > <mst@redhat.com> > Subject: Re: [Qemu-devel] [PATCH 1/3] x86/cpu: Enable > UMONITOR/UMWAIT/TPAUSE cpu features > > On Tue, Jul 10, 2018 at 04:57:32PM +0800, Jingqi Liu wrote: > > UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions. > > > > UMONITOR arms address monitoring hardware using an address. A store to > > an address within the specified address range triggers the monitoring > > hardware to wake up the processor waiting in umwait. > > > > UMWAIT instructs the processor to enter an implementation-dependent > > optimized state while monitoring a range of addresses. The optimized > > state may be either a light-weight power/performance optimized state > > or an improved power/performance optimized state. > > > > TPAUSE instructs the processor to enter an implementation-dependent > > optimized state c0.1 or c0.2 state and wake up when time-stamp counter > > reaches specified timeout. > > > > The bit definition: > > CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG > > > > The release document ref below link: > > https://software.intel.com/sites/default/files/managed/c5/15/\ > > architecture-instruction-set-extensions-programming-reference.pdf > > > > Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> > > Is it really OK to expose these features to the guest without "-overcommit cpu- > pm=on"? > > Don't we need code to migrate IA32_UMWAIT_CONTROL? > > (I don't see code to handle writes to IA32_UMWAIT_CONTROL on the KVM > patches, either.) > > -- Hi Eduardo, Yes, I'll handle IA32_UMWAIT_CONTROL in the second version. Thanks for your review. > Eduardo
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0e2f2e..e0d151f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -978,7 +978,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_7_0_ECX] = { .feat_names = { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, NULL, "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2c5a0d9..f651105 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -674,6 +674,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_UMIP (1U << 2) #define CPUID_7_0_ECX_PKU (1U << 3) #define CPUID_7_0_ECX_OSPKE (1U << 4) +#define CPUID_7_0_ECX_WAITPKG (1U << 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */ #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */ #define CPUID_7_0_ECX_GFNI (1U << 8) #define CPUID_7_0_ECX_VAES (1U << 9)
UMONITOR, UMWAIT, and TPAUSE are a set of user wait instructions. UMONITOR arms address monitoring hardware using an address. A store to an address within the specified address range triggers the monitoring hardware to wake up the processor waiting in umwait. UMWAIT instructs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The optimized state may be either a light-weight power/performance optimized state or an improved power/performance optimized state. TPAUSE instructs the processor to enter an implementation-dependent optimized state c0.1 or c0.2 state and wake up when time-stamp counter reaches specified timeout. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 05] WAITPKG The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)