@@ -51,15 +51,6 @@ config TARGET_VCT
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select ROM_EXCEPTION_VECTORS
-config TARGET_PB1X00
- bool "Support pb1x00"
- select SUPPORTS_LITTLE_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select SYS_MIPS_CACHE_INIT_RAM_LOAD
- select ROM_EXCEPTION_VECTORS
- select MIPS_TUNE_4KC
-
config ARCH_ATH79
bool "Support QCA/Atheros ath79"
select OF_CONTROL
@@ -119,7 +110,6 @@ source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
-source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
@@ -11,7 +11,6 @@ endif
libs-y += arch/mips/cpu/
libs-y += arch/mips/lib/
-machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
@@ -130,13 +130,13 @@
* Returns the uncached address of a sdram address
*/
#ifndef __ASSEMBLY__
-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_TB0229)
/* We use a 36 bit physical address map here and
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else /* !CONFIG_SOC_AU1X00 */
+#else /* !CONFIG_TB0229 */
#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
-#endif /* CONFIG_SOC_AU1X00 */
+#endif /* CONFIG_TB0229 */
#endif /* __ASSEMBLY__ */
/*
deleted file mode 100644
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2011
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
deleted file mode 100644
@@ -1,307 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Only eth0 supported for now
- *
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-#include <config.h>
-
-#if defined(CONFIG_SYS_DISCOVER_PHY)
-#error "PHY not supported yet"
-/* We just assume that we are running 100FD for now */
-/* We all use switches, right? ;-) */
-#endif
-
-/* I assume ethernet behaves like au1000 */
-
-#ifdef CONFIG_SOC_AU1000
-/* Base address differ between cpu:s */
-#define ETH0_BASE AU1000_ETH0_BASE
-#define MAC0_ENABLE AU1000_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1100
-#define ETH0_BASE AU1100_ETH0_BASE
-#define MAC0_ENABLE AU1100_MAC0_ENABLE
-#else
-#ifdef CONFIG_SOC_AU1500
-#define ETH0_BASE AU1500_ETH0_BASE
-#define MAC0_ENABLE AU1500_MAC0_ENABLE
-#else
-#error "No valid cpu set"
-#endif
-#endif
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <command.h>
-#include <asm/io.h>
-#include <mach/au1x00.h>
-
-#if defined(CONFIG_CMD_MII)
-#include <miiphy.h>
-#endif
-
-/* Ethernet Transmit and Receive Buffers */
-#define DBUF_LENGTH 1520
-#define PKT_MAXBUF_SIZE 1518
-
-static char txbuf[DBUF_LENGTH];
-
-static int next_tx;
-static int next_rx;
-
-/* 4 rx and 4 tx fifos */
-#define NO_OF_FIFOS 4
-
-typedef struct{
- u32 status;
- u32 addr;
- u32 len; /* Only used for tx */
- u32 not_used;
-} mac_fifo_t;
-
-mac_fifo_t mac_fifo[NO_OF_FIFOS];
-
-#define MAX_WAIT 1000
-
-#if defined(CONFIG_CMD_MII)
-int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
-{
- unsigned short value = 0;
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ;
-
- *mii_control_reg = mii_control;
-
- timedout = 20;
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_read busy timeout!!\n");
- return -1;
- }
- }
- value = *mii_data_reg;
- return value;
-}
-
-int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg,
- u16 value)
-{
- volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL);
- volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA);
- u32 mii_control;
- unsigned int timedout = 20;
-
- while (*mii_control_reg & MAC_MII_BUSY) {
- udelay(1000);
- if (--timedout == 0) {
- printf("au1x00_eth: miiphy_write busy timeout!!\n");
- return -1;
- }
- }
-
- mii_control = MAC_SET_MII_SELECT_REG(reg) |
- MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE;
-
- *mii_data_reg = value;
- *mii_control_reg = mii_control;
- return 0;
-}
-#endif
-
-static int au1x00_send(struct eth_device *dev, void *packet, int length)
-{
- volatile mac_fifo_t *fifo_tx =
- (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
- int i;
- int res;
-
- /* tx fifo should always be idle */
- fifo_tx[next_tx].len = length;
- fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
- au_sync();
-
- udelay(1);
- i=0;
- while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
- if(i>MAX_WAIT){
- printf("TX timeout\n");
- break;
- }
- udelay(1);
- i++;
- }
-
- /* Clear done bit */
- fifo_tx[next_tx].addr = 0;
- fifo_tx[next_tx].len = 0;
- au_sync();
-
- res = fifo_tx[next_tx].status;
-
- next_tx++;
- if(next_tx>=NO_OF_FIFOS){
- next_tx=0;
- }
- return(res);
-}
-
-static int au1x00_recv(struct eth_device* dev){
- volatile mac_fifo_t *fifo_rx =
- (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
-
- int length;
- u32 status;
-
- for(;;){
- if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
- /* Nothing has been received */
- return(-1);
- }
-
- status = fifo_rx[next_rx].status;
-
- length = status&0x3FFF;
-
- if(status&RX_ERROR){
- printf("Rx error 0x%x\n", status);
- } else {
- /* Pass the packet up to the protocol layers. */
- net_process_received_packet(net_rx_packets[next_rx],
- length - 4);
- }
-
- fifo_rx[next_rx].addr =
- (virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
-
- next_rx++;
- if(next_rx>=NO_OF_FIFOS){
- next_rx=0;
- }
- } /* for */
-
- return(0); /* Does anyone use this? */
-}
-
-static int au1x00_init(struct eth_device* dev, bd_t * bd){
-
- volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
- volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
- volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
- volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
- volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
- volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
- volatile mac_fifo_t *fifo_tx =
- (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
- volatile mac_fifo_t *fifo_rx =
- (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
- int i;
-
- next_tx = TX_GET_DMA_BUFFER(fifo_tx[0].addr);
- next_rx = RX_GET_DMA_BUFFER(fifo_rx[0].addr);
-
- /* We have to enable clocks before releasing reset */
- *macen = MAC_EN_CLOCK_ENABLE;
- udelay(10);
-
- /* Enable MAC0 */
- /* We have to release reset before accessing registers */
- *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
- MAC_EN_RESET1|MAC_EN_RESET2;
- udelay(10);
-
- for(i=0;i<NO_OF_FIFOS;i++){
- fifo_tx[i].len = 0;
- fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
- fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
- RX_DMA_ENABLE;
- }
-
- /* Put mac addr in little endian */
-#define ea eth_get_ethaddr()
- *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
- *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
- (ea[1] << 8) | (ea[0] ) ;
-#undef ea
- *mac_mcast_low = 0;
- *mac_mcast_high = 0;
-
- /* Make sure the MAC buffer is in the correct endian mode */
-#ifdef __LITTLE_ENDIAN
- *mac_ctrl = MAC_FULL_DUPLEX;
- udelay(1);
- *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#else
- *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
- udelay(1);
- *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
-#endif
-
- return(1);
-}
-
-static void au1x00_halt(struct eth_device* dev){
- volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
-
- /* Put MAC0 in reset */
- *macen = 0;
-}
-
-int au1x00_enet_initialize(bd_t *bis){
- struct eth_device* dev;
-
- if ((dev = (struct eth_device*)malloc(sizeof *dev)) == NULL) {
- puts ("malloc failed\n");
- return -1;
- }
-
- memset(dev, 0, sizeof *dev);
-
- strcpy(dev->name, "Au1X00 ethernet");
- dev->iobase = 0;
- dev->priv = 0;
- dev->init = au1x00_init;
- dev->halt = au1x00_halt;
- dev->send = au1x00_send;
- dev->recv = au1x00_recv;
-
- eth_register(dev);
-
-#if defined(CONFIG_CMD_MII)
- int retval;
- struct mii_dev *mdiodev = mdio_alloc();
- if (!mdiodev)
- return -ENOMEM;
- strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
- mdiodev->read = au1x00_miiphy_read;
- mdiodev->write = au1x00_miiphy_write;
-
- retval = mdio_register(mdiodev);
- if (retval < 0)
- return retval;
-#endif
-
- return 1;
-}
-
-int cpu_eth_init(bd_t *bis)
-{
- au1x00_enet_initialize(bis);
- return 0;
-}
deleted file mode 100644
@@ -1,14 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2000-2011
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-#include <ide.h>
-
-/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
-void ide_input_swap_data(int dev, ulong *sect_buf, int words)
-{
- ide_input_data(dev, sect_buf, words);
-}
deleted file mode 100644
@@ -1,130 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * AU1X00 UART support
- *
- * Hardcoded to UART 0 for now
- * Speed and options also hardcoded to 115200 8N1
- *
- * Copyright (c) 2003 Thomas.Lange@corelatus.se
- */
-
-#include <config.h>
-#include <common.h>
-#include <mach/au1x00.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-/******************************************************************************
-*
-* serial_init - initialize a channel
-*
-* This routine initializes the number of data bits, parity
-* and set the selected baud rate. Interrupts are disabled.
-* Set the modem control signals if the option is selected.
-*
-* RETURNS: N/A
-*/
-
-static int au1x00_serial_init(void)
-{
- volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
- volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
-
- /* Enable clocks first */
- *uart_enable = UART_EN_CE;
-
- /* Then release reset */
- /* Must release reset before setting other regs */
- *uart_enable = UART_EN_CE|UART_EN_E;
-
- /* Activate fifos, reset tx and rx */
- /* Set tx trigger level to 12 */
- *uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
- UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
-
- serial_setbrg();
-
- return 0;
-}
-
-
-static void au1x00_serial_setbrg(void)
-{
- volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
- volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
- volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
- int sd;
- int divisorx2;
-
- /* sd is system clock divisor */
- /* see section 10.4.5 in au1550 datasheet */
- sd = (*sys_powerctrl & 0x03) + 2;
-
- /* calulate 2x baudrate and round */
- divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
-
- if (divisorx2 & 0x01)
- divisorx2 = divisorx2 + 1;
-
- *uart_clk = divisorx2 / 2;
-
- /* Set parity, stop bits and word length to 8N1 */
- *uart_lcr = UART_LCR_WLEN8;
-}
-
-static void au1x00_serial_putc(const char c)
-{
- volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
- volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
-
- if (c == '\n')
- au1x00_serial_putc('\r');
-
- /* Wait for fifo to shift out some bytes */
- while((*uart_lsr&UART_LSR_THRE)==0);
-
- *uart_tx = (u32)c;
-}
-
-static int au1x00_serial_getc(void)
-{
- volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
- char c;
-
- while (!serial_tstc());
-
- c = (*uart_rx&0xFF);
- return c;
-}
-
-static int au1x00_serial_tstc(void)
-{
- volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
-
- if(*uart_lsr&UART_LSR_DR){
- /* Data in rfifo */
- return(1);
- }
- return 0;
-}
-
-static struct serial_device au1x00_serial_drv = {
- .name = "au1x00_serial",
- .start = au1x00_serial_init,
- .stop = NULL,
- .setbrg = au1x00_serial_setbrg,
- .putc = au1x00_serial_putc,
- .puts = default_serial_puts,
- .getc = au1x00_serial_getc,
- .tstc = au1x00_serial_tstc,
-};
-
-void au1x00_serial_initialize(void)
-{
- serial_register(&au1x00_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &au1x00_serial_drv;
-}
deleted file mode 100644
@@ -1,1609 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- * Note: Part of this code has been derived from linux
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <config.h>
-
-#ifdef CONFIG_USB_OHCI
-
-/* #include <pci.h> no PCI on the AU1x00 */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <mach/au1x00.h>
-#include <usb.h>
-#include "au1x00_usb_ohci.h"
-
-#define OHCI_USE_NPS /* force NoPowerSwitching mode */
-#define OHCI_VERBOSE_DEBUG /* not always helpful */
-#define OHCI_FILL_TRACE
-
-#define USBH_ENABLE_BE (1<<0)
-#define USBH_ENABLE_C (1<<1)
-#define USBH_ENABLE_E (1<<2)
-#define USBH_ENABLE_CE (1<<3)
-#define USBH_ENABLE_RD (1<<4)
-
-#ifdef __LITTLE_ENDIAN
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
-#else
-#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
-#endif
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define OHCI_CONTROL_INIT \
- (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#undef readl
-#undef writel
-
-#define readl(a) au_readl((long)(a))
-#define writel(v,a) au_writel((v),(int)(a))
-
-#define DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#define SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global ohci_t */
-static ohci_t gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-urb_priv_t urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect. AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
- u32 temp = readl (&hc->regs->roothub.register); \
- if (hc->flags & OHCI_QUIRK_AMD756) \
- while (temp & mask) \
- temp = readl (&hc->regs->roothub.register); \
- temp; })
-
-static u32 roothub_a (struct ohci *hc)
- { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
- { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
- { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
- { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
-
-/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv (urb_priv_t * urb)
-{
- int i;
- int last;
- struct td * td;
-
- last = urb->length - 1;
- if (last >= 0) {
- for (i = 0; i <= last; i++) {
- td = urb->td[i];
- if (td) {
- td->usb_dev = NULL;
- urb->td[i] = NULL;
- }
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, char * str, int small)
-{
- urb_priv_t * purb = &urb_priv;
-
- dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
- str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
-#ifdef OHCI_VERBOSE_DEBUG
- if (!small) {
- int i, len;
-
- if (usb_pipecontrol (pipe)) {
- printf (__FILE__ ": cmd(8):");
- for (i = 0; i < 8 ; i++)
- printf (" %02x", ((__u8 *) setup) [i]);
- printf ("\n");
- }
- if (transfer_len > 0 && buffer) {
- printf (__FILE__ ": data(%d/%d):",
- purb->actual_length,
- transfer_len);
- len = usb_pipeout (pipe)?
- transfer_len: purb->actual_length;
- for (i = 0; i < 16 && i < len; i++)
- printf (" %02x", ((__u8 *) buffer) [i]);
- printf ("%s\n", i < len? "...": "");
- }
- }
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
- int i, j;
- __u32 * ed_p;
- for (i= 0; i < 32; i++) {
- j = 5;
- ed_p = &(ohci->hcca->int_table [i]);
- if (*ed_p == 0)
- continue;
- printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
- while (*ed_p != 0 && j--) {
- ed_t *ed = (ed_t *)m32_swap(ed_p);
- printf (" ed: %4x;", ed->hwINFO);
- ed_p = &ed->hwNextED;
- }
- printf ("\n");
- }
-}
-
-static void ohci_dump_intr_mask (char *label, __u32 mask)
-{
- dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
- label,
- mask,
- (mask & OHCI_INTR_MIE) ? " MIE" : "",
- (mask & OHCI_INTR_OC) ? " OC" : "",
- (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
- (mask & OHCI_INTR_FNO) ? " FNO" : "",
- (mask & OHCI_INTR_UE) ? " UE" : "",
- (mask & OHCI_INTR_RD) ? " RD" : "",
- (mask & OHCI_INTR_SF) ? " SF" : "",
- (mask & OHCI_INTR_WDH) ? " WDH" : "",
- (mask & OHCI_INTR_SO) ? " SO" : ""
- );
-}
-
-static void maybe_print_eds (char *label, __u32 value)
-{
- ed_t *edp = (ed_t *)value;
-
- if (value) {
- dbg ("%s %08x", label, value);
- dbg ("%08x", edp->hwINFO);
- dbg ("%08x", edp->hwTailP);
- dbg ("%08x", edp->hwHeadP);
- dbg ("%08x", edp->hwNextED);
- }
-}
-
-static char * hcfs2string (int state)
-{
- switch (state) {
- case OHCI_USB_RESET: return "reset";
- case OHCI_USB_RESUME: return "resume";
- case OHCI_USB_OPER: return "operational";
- case OHCI_USB_SUSPEND: return "suspend";
- }
- return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
-{
- struct ohci_regs *regs = controller->regs;
- __u32 temp;
-
- temp = readl (®s->revision) & 0xff;
- if (temp != 0x10)
- dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
- temp = readl (®s->control);
- dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
- (temp & OHCI_CTRL_RWE) ? " RWE" : "",
- (temp & OHCI_CTRL_RWC) ? " RWC" : "",
- (temp & OHCI_CTRL_IR) ? " IR" : "",
- hcfs2string (temp & OHCI_CTRL_HCFS),
- (temp & OHCI_CTRL_BLE) ? " BLE" : "",
- (temp & OHCI_CTRL_CLE) ? " CLE" : "",
- (temp & OHCI_CTRL_IE) ? " IE" : "",
- (temp & OHCI_CTRL_PLE) ? " PLE" : "",
- temp & OHCI_CTRL_CBSR
- );
-
- temp = readl (®s->cmdstatus);
- dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
- (temp & OHCI_SOC) >> 16,
- (temp & OHCI_OCR) ? " OCR" : "",
- (temp & OHCI_BLF) ? " BLF" : "",
- (temp & OHCI_CLF) ? " CLF" : "",
- (temp & OHCI_HCR) ? " HCR" : ""
- );
-
- ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
- ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
-
- maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
-
- maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
- maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
-
- maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
- maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
-
- maybe_print_eds ("donehead", readl (®s->donehead));
-}
-
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
-{
- __u32 temp, ndp, i;
-
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
-
- if (verbose) {
- dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
- ((temp & RH_A_POTPGT) >> 24) & 0xff,
- (temp & RH_A_NOCP) ? " NOCP" : "",
- (temp & RH_A_OCPM) ? " OCPM" : "",
- (temp & RH_A_DT) ? " DT" : "",
- (temp & RH_A_NPS) ? " NPS" : "",
- (temp & RH_A_PSM) ? " PSM" : "",
- ndp
- );
- temp = roothub_b (controller);
- dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
- temp,
- (temp & RH_B_PPCM) >> 16,
- (temp & RH_B_DR)
- );
- temp = roothub_status (controller);
- dbg ("roothub.status: %08x%s%s%s%s%s%s",
- temp,
- (temp & RH_HS_CRWE) ? " CRWE" : "",
- (temp & RH_HS_OCIC) ? " OCIC" : "",
- (temp & RH_HS_LPSC) ? " LPSC" : "",
- (temp & RH_HS_DRWE) ? " DRWE" : "",
- (temp & RH_HS_OCI) ? " OCI" : "",
- (temp & RH_HS_LPS) ? " LPS" : ""
- );
- }
-
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
- i,
- temp,
- (temp & RH_PS_PRSC) ? " PRSC" : "",
- (temp & RH_PS_OCIC) ? " OCIC" : "",
- (temp & RH_PS_PSSC) ? " PSSC" : "",
- (temp & RH_PS_PESC) ? " PESC" : "",
- (temp & RH_PS_CSC) ? " CSC" : "",
-
- (temp & RH_PS_LSDA) ? " LSDA" : "",
- (temp & RH_PS_PPS) ? " PPS" : "",
- (temp & RH_PS_PRS) ? " PRS" : "",
- (temp & RH_PS_POCI) ? " POCI" : "",
- (temp & RH_PS_PSS) ? " PSS" : "",
-
- (temp & RH_PS_PES) ? " PES" : "",
- (temp & RH_PS_CCS) ? " CCS" : ""
- );
- }
-}
-
-static void ohci_dump (ohci_t *controller, int verbose)
-{
- dbg ("OHCI controller usb-%s state", controller->slot_name);
-
- /* dumps some of the state we know about */
- ohci_dump_status (controller);
- if (verbose)
- ep_print_int_eds (controller, "hcca");
- dbg ("hcca frame #%04x", controller->hcca->frame_no);
- ohci_dump_roothub (controller, 1);
-}
-
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- ohci_t *ohci;
- ed_t * ed;
- urb_priv_t *purb_priv;
- int i, size = 0;
-
- ohci = &gohci;
-
- /* when controller's hung, permit only roothub cleanup attempts
- * such as powering down ports */
- if (ohci->disabled) {
- err("sohci_submit_job: EPIPE");
- return -1;
- }
-
- /* every endpoint has a ed, locate and fill it */
- if (!(ed = ep_add_ed (dev, pipe))) {
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
-
- /* for the private part of the URB we need the number of TDs (size) */
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK: /* one TD for every 4096 Byte */
- size = (transfer_len - 1) / 4096 + 1;
- break;
- case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
- size = (transfer_len == 0)? 2:
- (transfer_len - 1) / 4096 + 3;
- break;
- }
-
- if (size >= (N_URB_TD - 1)) {
- err("need %d TDs, only have %d", size, N_URB_TD);
- return -1;
- }
- purb_priv = &urb_priv;
- purb_priv->pipe = pipe;
-
- /* fill the private part of the URB */
- purb_priv->length = size;
- purb_priv->ed = ed;
- purb_priv->actual_length = 0;
-
- /* allocate the TDs */
- /* note that td[0] was allocated in ep_add_ed */
- for (i = 0; i < size; i++) {
- purb_priv->td[i] = td_alloc (dev);
- if (!purb_priv->td[i]) {
- purb_priv->length = i;
- urb_free_priv (purb_priv);
- err("sohci_submit_job: ENOMEM");
- return -1;
- }
- }
-
- if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
- urb_free_priv (purb_priv);
- err("sohci_submit_job: EINVAL");
- return -1;
- }
-
- /* link the ed into a chain if is not already */
- if (ed->state != ED_OPER)
- ep_link (ohci, ed);
-
- /* fill the TDs and link it to the ed */
- td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
-{
- ohci_t *ohci = &gohci;
-
- return m16_swap (ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link (ohci_t *ohci, ed_t *edi)
-{
- volatile ed_t *ed = edi;
-
- ed->state = ED_OPER;
-
- switch (ed->type) {
- case PIPE_CONTROL:
- ed->hwNextED = 0;
- if (ohci->ed_controltail == NULL) {
- writel ((long)ed, &ohci->regs->ed_controlhead);
- } else {
- ohci->ed_controltail->hwNextED = m32_swap (ed);
- }
- ed->ed_prev = ohci->ed_controltail;
- if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_controltail = edi;
- break;
-
- case PIPE_BULK:
- ed->hwNextED = 0;
- if (ohci->ed_bulktail == NULL) {
- writel ((long)ed, &ohci->regs->ed_bulkhead);
- } else {
- ohci->ed_bulktail->hwNextED = m32_swap (ed);
- }
- ed->ed_prev = ohci->ed_bulktail;
- if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
- ohci->hc_control |= OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- ohci->ed_bulktail = edi;
- break;
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
-{
- ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
-
- switch (ed->type) {
- case PIPE_CONTROL:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_controltail == ed) {
- ohci->ed_controltail = ed->ed_prev;
- } else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
-
- case PIPE_BULK:
- if (ed->ed_prev == NULL) {
- if (!ed->hwNextED) {
- ohci->hc_control &= ~OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
- }
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
- } else {
- ed->ed_prev->hwNextED = ed->hwNextED;
- }
- if (ohci->ed_bulktail == ed) {
- ohci->ed_bulktail = ed->ed_prev;
- } else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
- }
- break;
- }
- ed->state = ED_UNLINK;
- return 0;
-}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
-
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
-{
- td_t *td;
- ed_t *ed_ret;
- volatile ed_t *ed;
-
- ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
- (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
-
- if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
- err("ep_add_ed: pending delete");
- /* pending delete request */
- return NULL;
- }
-
- if (ed->state == ED_NEW) {
- ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
- /* dummy td; end of td list for ed */
- td = td_alloc (usb_dev);
- ed->hwTailP = m32_swap (td);
- ed->hwHeadP = ed->hwTailP;
- ed->state = ED_UNLINK;
- ed->type = usb_pipetype (pipe);
- ohci_dev.ed_cnt++;
- }
-
- ed->hwINFO = m32_swap (usb_pipedevice (pipe)
- | usb_pipeendpoint (pipe) << 7
- | (usb_pipeisoc (pipe)? 0x8000: 0)
- | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
- | (usb_dev->speed == USB_SPEED_LOW) << 13
- | usb_maxpacket (usb_dev, pipe) << 16);
-
- return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill (ohci_t *ohci, unsigned int info,
- void *data, int len,
- struct usb_device *dev, int index, urb_priv_t *urb_priv)
-{
- volatile td_t *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
- int i;
-#endif
-
- if (index > urb_priv->length) {
- err("index > length");
- return;
- }
- /* use this td as the next dummy */
- td_pt = urb_priv->td [index];
- td_pt->hwNextTD = 0;
-
- /* fill the old dummy TD */
- td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
-
- td->ed = urb_priv->ed;
- td->next_dl_td = NULL;
- td->index = index;
- td->data = (__u32)data;
-#ifdef OHCI_FILL_TRACE
- if (1 || (usb_pipebulk(urb_priv->pipe) &&
- usb_pipeout(urb_priv->pipe))) {
- for (i = 0; i < len; i++)
- printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
- }
-#endif
- if (!len)
- data = 0;
-
- td->hwINFO = m32_swap (info);
- td->hwCBP = m32_swap (data);
- if (data)
- td->hwBE = m32_swap (data + len - 1);
- else
- td->hwBE = 0;
- td->hwNextTD = m32_swap (td_pt);
- td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
-
- /* append to queue */
- td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
-
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
-{
- ohci_t *ohci = &gohci;
- int data_len = transfer_len;
- void *data;
- int cnt = 0;
- __u32 info = 0;
- unsigned int toggle = 0;
-
- /* OHCI handles the DATA-toggles itself, we just use the
- USB-toggle bits for resetting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
- toggle = TD_T_TOGGLE;
- } else {
- toggle = TD_T_DATA0;
- usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
- }
- urb->td_cnt = 0;
- if (data_len)
- data = kseg_to_phys(buffer);
- else
- data = 0;
-
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK:
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
- while(data_len > 4096) {
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
- data += 4096; data_len -= 4096; cnt++;
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
- cnt++;
-
- if (!ohci->sleeping)
- writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
- break;
-
- case PIPE_CONTROL:
- info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
- td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
- if (data_len > 0) {
- info = usb_pipeout (pipe)?
- TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
- /* NOTE: mishandles transfers >8K, some >4K */
- td_fill (ohci, info, data, data_len, dev, cnt++, urb);
- }
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
- td_fill (ohci, info, data, 0, dev, cnt++, urb);
- if (!ohci->sleeping)
- writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
- break;
- }
- if (urb->length != cnt)
- dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(td_t * td)
-{
- __u32 tdINFO, tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
-
- tdINFO = m32_swap (td->hwINFO);
- tdBE = m32_swap (td->hwBE);
- tdCBP = m32_swap (td->hwCBP);
-
-
- if (!(usb_pipecontrol(lurb_priv->pipe) &&
- ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
- if (tdBE != 0) {
- if (td->hwCBP == 0)
- lurb_priv->actual_length += tdBE - td->data + 1;
- else
- lurb_priv->actual_length += tdCBP - td->data;
- }
- }
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static td_t * dl_reverse_done_list (ohci_t *ohci)
-{
- __u32 td_list_hc;
- td_t *td_rev = NULL;
- td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
-
- td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
- ohci->hcca->done_head = 0;
-
- while (td_list_hc) {
- td_list = (td_t *)td_list_hc;
-
- if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
- lurb_priv = &urb_priv;
- dbg(" USB-error/status: %x : %p",
- TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & m32_swap (0x1)) {
- if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
- td_list->ed->hwHeadP =
- (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
- (td_list->ed->hwHeadP & m32_swap (0x2));
- lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
- } else
- td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
- }
- }
-
- td_list->next_dl_td = td_rev;
- td_rev = td_list;
- td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
- }
- return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
-{
- td_t *td_list_next = NULL;
- ed_t *ed;
- int cc = 0;
- int stat = 0;
- /* urb_t *urb; */
- urb_priv_t *lurb_priv;
- __u32 tdINFO, edHeadP, edTailP;
-
- while (td_list) {
- td_list_next = td_list->next_dl_td;
-
- lurb_priv = &urb_priv;
- tdINFO = m32_swap (td_list->hwINFO);
-
- ed = td_list->ed;
-
- dl_transfer_length(td_list);
-
- /* error code of transfer */
- cc = TD_CC_GET (tdINFO);
- if (cc != 0) {
- dbg("ConditionCode %#x", cc);
- stat = cc_to_error[cc];
- }
-
- if (ed->state != ED_NEW) {
- edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap (ed->hwTailP);
-
- /* unlink eds if they are not busy */
- if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
- }
-
- td_list = td_list_next;
- }
- return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-#include <usbroothubdes.h>
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x) len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
-#else
-#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT roothub_status(&gohci)
-#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(ohci_t *controller)
-{
- __u32 temp, ndp, i;
- int res;
-
- res = -1;
- temp = roothub_a (controller);
- ndp = (temp & RH_A_NDP);
- for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- /* check for a device disconnect */
- if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) &&
- ((temp & RH_PS_CCS) == 0)) {
- res = i;
- break;
- }
- }
- return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
-{
- void * data = buffer;
- int leni = transfer_len;
- int len = 0;
- int stat = 0;
- __u32 datab[4];
- __u8 *data_buf = (__u8 *)datab;
- __u16 bmRType_bReq;
- __u16 wValue;
- __u16 wIndex;
- __u16 wLength;
-
-#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (usb_pipeint(pipe)) {
- info("Root-Hub submit IRQ: NOT implemented");
- return 0;
- }
-
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = m16_swap (cmd->value);
- wIndex = m16_swap (cmd->index);
- wLength = m16_swap (cmd->length);
-
- info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
- dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
- switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
-
- case RH_GET_STATUS:
- *(__u16 *) data_buf = m16_swap (1); OK (2);
- case RH_GET_STATUS | RH_INTERFACE:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_ENDPOINT:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
- case RH_GET_STATUS | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (
- RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
- OK (4);
- case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
-
- case RH_CLEAR_FEATURE | RH_ENDPOINT:
- switch (wValue) {
- case (RH_ENDPOINT_STALL): OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_CLASS:
- switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- OK(0);
- case (RH_C_HUB_OVER_CURRENT):
- WR_RH_STAT(RH_HS_OCIC); OK (0);
- }
- break;
-
- case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
- case (RH_C_PORT_CONNECTION):
- WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
- case (RH_C_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
- case (RH_C_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
- case (RH_C_PORT_OVER_CURRENT):
- WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
- case (RH_C_PORT_RESET):
- WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
- }
- break;
-
- case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
- switch (wValue) {
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
- case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PRS);
- OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
- case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PES );
- OK (0);
- }
- break;
-
- case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
-
- case RH_GET_DESCRIPTOR:
- switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des; OK(len);
- case (0x02): /* configuration descriptor */
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des; OK(len);
- case (0x03): /* string descriptors */
- if(wValue==0x0300) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- OK(len);
- }
- if(wValue==0x0301) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- OK(len);
- }
- default:
- stat = USB_ST_STALLED;
- }
- break;
-
- case RH_GET_DESCRIPTOR | RH_CLASS:
- {
- __u32 temp = roothub_a (&gohci);
-
- data_buf [0] = 9; /* min length; */
- data_buf [1] = 0x29;
- data_buf [2] = temp & RH_A_NDP;
- data_buf [3] = 0;
- if (temp & RH_A_PSM) /* per-port power switching? */
- data_buf [3] |= 0x1;
- if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf [3] |= 0x10;
- else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
- data_buf [3] |= 0x8;
-
- /* corresponds to data_buf[4-7] */
- datab [1] = 0;
- data_buf [5] = (temp & RH_A_POTPGT) >> 24;
- temp = roothub_b (&gohci);
- data_buf [7] = temp & RH_B_DR;
- if (data_buf [2] < 7) {
- data_buf [8] = 0xff;
- } else {
- data_buf [0] += 2;
- data_buf [8] = (temp & RH_B_DR) >> 8;
- data_buf [10] = data_buf [9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf [0], wLength));
- OK (len);
- }
-
- case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
-
- case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
-
- default:
- dbg ("unsupported root hub command");
- stat = USB_ST_STALLED;
- }
-
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#else
- mdelay(1);
-#endif
-
- len = min_t(int, len, leni);
- if (data != data_buf)
- memcpy (data, data_buf, len);
- dev->act_len = len;
- dev->status = stat;
-
-#ifdef DEBUG
- if (transfer_len)
- urb_priv.actual_length = transfer_len;
- pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
-#else
- mdelay(1);
-#endif
-
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
-{
- int stat = 0;
- int maxsize = usb_maxpacket(dev, pipe);
- int timeout;
-
- /* device pulled? Shortcut the action. */
- if (devgone == dev) {
- dev->status = USB_ST_CRC_ERR;
- return 0;
- }
-
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (!maxsize) {
- err("submit_common_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
-
- if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
- err("sohci_submit_job failed");
- return -1;
- }
-
- mdelay(10);
- /* ohci_dump_status(&gohci); */
-
- /* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
- if (usb_pipebulk(pipe))
- timeout = BULK_TO;
- else
- timeout = 100;
-
- timeout *= 4;
- /* wait for it to complete */
- for (;;) {
- /* check whether the controller is done */
- stat = hc_interrupt();
- if (stat < 0) {
- stat = USB_ST_CRC_ERR;
- break;
- }
- if (stat >= 0 && stat != 0xff) {
- /* 0xff is returned for an SF-interrupt */
- break;
- }
- if (--timeout) {
- udelay(250); /* mdelay(1); */
- } else {
- err("CTL:TIMEOUT ");
- stat = USB_ST_CRC_ERR;
- break;
- }
- }
- /* we got an Root Hub Status Change interrupt */
- if (got_rhsc) {
-#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
-#endif
- got_rhsc = 0;
- /* abuse timeout */
- timeout = rh_check_port_status(&gohci);
- if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
- /* the called routine adds 1 to the passed value */
- usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
- /*
- * XXX
- * This is potentially dangerous because it assumes
- * that only one device is ever plugged in!
- */
- devgone = dev;
- }
- }
-
- dev->status = stat;
- dev->act_len = transfer_len;
-
-#ifdef DEBUG
- pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
-
- /* free TDs in urb_priv */
- urb_free_priv (&urb_priv);
- return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
-{
- info("submit_bulk_msg");
- return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
-{
- int maxsize = usb_maxpacket(dev, pipe);
-
- info("submit_control_msg");
-#ifdef DEBUG
- urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
-#else
- mdelay(1);
-#endif
- if (!maxsize) {
- err("submit_control_message: pipesize for pipe %lx is zero",
- pipe);
- return -1;
- }
- if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
- gohci.rh.dev = dev;
- /* root hub - redirect */
- return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
- }
-
- return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
-{
- info("submit_int_msg");
- return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset (ohci_t *ohci)
-{
- int timeout = 30;
- int smm_timeout = 50; /* 0,5 sec */
-
- if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
- writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
- info("USB HC TakeOver from SMM");
- while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
- mdelay (10);
- if (--smm_timeout == 0) {
- err("USB HC TakeOver failed!");
- return -1;
- }
- }
- }
-
- /* Disable HC interrupts */
- writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
- dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
- ohci->slot_name,
- readl (&ohci->regs->control));
-
- /* Reset USB (needed by some controllers) */
- writel (0, &ohci->regs->control);
-
- /* HC Reset requires max 10 us delay */
- writel (OHCI_HCR, &ohci->regs->cmdstatus);
- while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
- if (--timeout == 0) {
- err("USB HC reset timed out!");
- return -1;
- }
- udelay (1);
- }
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start (ohci_t * ohci)
-{
- __u32 mask;
- unsigned int fminterval;
-
- ohci->disabled = 1;
-
- /* Tell the controller where the control and bulk lists are
- * The lists are empty now. */
-
- writel (0, &ohci->regs->ed_controlhead);
- writel (0, &ohci->regs->ed_bulkhead);
-
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
-
- fminterval = 0x2edf;
- writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
- fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
- writel (fminterval, &ohci->regs->fminterval);
- writel (0x628, &ohci->regs->lsthresh);
-
- /* start controller operations */
- ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
- ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
-
- /* disable all interrupts */
- mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
- OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
- OHCI_INTR_OC | OHCI_INTR_MIE);
- writel (mask, &ohci->regs->intrdisable);
- /* clear all interrupts */
- mask &= ~OHCI_INTR_MIE;
- writel (mask, &ohci->regs->intrstatus);
- /* Choose the interrupts we care about now - but w/o MIE */
- mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
- writel (mask, &ohci->regs->intrenable);
-
-#ifdef OHCI_USE_NPS
- /* required for AMD-756 and some Mac platforms */
- writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
- &ohci->regs->roothub.a);
- writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
- /* POTPGT delay is bits 24-31, in 2 ms units. */
- mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
-
- /* connect the virtual root hub */
- ohci->rh.devnum = 0;
-
- return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int
-hc_interrupt (void)
-{
- ohci_t *ohci = &gohci;
- struct ohci_regs *regs = ohci->regs;
- int ints;
- int stat = -1;
-
- if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
- ints = OHCI_INTR_WDH;
- } else {
- ints = readl (®s->intrstatus);
- }
-
- /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
-
- if (ints & OHCI_INTR_RHSC) {
- got_rhsc = 1;
- }
-
- if (ints & OHCI_INTR_UE) {
- ohci->disabled++;
- err ("OHCI Unrecoverable Error, controller usb-%s disabled",
- ohci->slot_name);
- /* e.g. due to PCI Master/Target Abort */
-
-#ifdef DEBUG
- ohci_dump (ohci, 1);
-#else
- mdelay(1);
-#endif
- /* FIXME: be optimistic, hope that bug won't repeat often. */
- /* Make some non-interrupt context restart the controller. */
- /* Count and limit the retries though; either hardware or */
- /* software errors can go forever... */
- hc_reset (ohci);
- return -1;
- }
-
- if (ints & OHCI_INTR_WDH) {
- mdelay(1);
- writel (OHCI_INTR_WDH, ®s->intrdisable);
- stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
- writel (OHCI_INTR_WDH, ®s->intrenable);
- }
-
- if (ints & OHCI_INTR_SO) {
- dbg("USB Schedule overrun\n");
- writel (OHCI_INTR_SO, ®s->intrenable);
- stat = -1;
- }
-
- /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
- if (ints & OHCI_INTR_SF) {
- unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
- mdelay(1);
- writel (OHCI_INTR_SF, ®s->intrdisable);
- if (ohci->ed_rm_list[frame] != NULL)
- writel (OHCI_INTR_SF, ®s->intrenable);
- stat = 0xff;
- }
-
- writel (ints, ®s->intrstatus);
- return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci (ohci_t *ohci)
-{
- dbg ("USB HC release ohci usb-%s", ohci->slot_name);
-
- if (!ohci->disabled)
- hc_reset (ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-#define __read_32bit_c0_register(source, sel) \
-({ int __res; \
- if (sel == 0) \
- __asm__ __volatile__( \
- "mfc0\t%0, " #source "\n\t" \
- : "=r" (__res)); \
- else \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "mfc0\t%0, " #source ", " #sel "\n\t" \
- ".set\tmips0\n\t" \
- : "=r" (__res)); \
- __res; \
-})
-
-#define read_c0_prid() __read_32bit_c0_register($15, 0)
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
-{
- u32 pin_func;
- u32 sys_freqctrl, sys_clksrc;
- u32 prid = read_c0_prid();
-
- dbg("in usb_lowlevel_init\n");
-
- /* zero and disable FREQ2 */
- sys_freqctrl = au_readl(SYS_FREQCTRL0);
- sys_freqctrl &= ~0xFFF00000;
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
- /* zero and disable USBH/USBD clocks */
- sys_clksrc = au_readl(SYS_CLKSRC);
- sys_clksrc &= ~0x00007FE0;
- au_writel(sys_clksrc, SYS_CLKSRC);
-
- sys_freqctrl = au_readl(SYS_FREQCTRL0);
- sys_freqctrl &= ~0xFFF00000;
-
- sys_clksrc = au_readl(SYS_CLKSRC);
- sys_clksrc &= ~0x00007FE0;
-
- switch (prid & 0x000000FF) {
- case 0x00: /* DA */
- case 0x01: /* HA */
- case 0x02: /* HB */
- /* CPU core freq to 48MHz to slow it way down... */
- au_writel(4, SYS_CPUPLL);
-
- /*
- * Setup 48MHz FREQ2 from CPUPLL for USB Host
- */
- /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
- sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
-
- /* CPU core freq to 384MHz */
- au_writel(0x20, SYS_CPUPLL);
-
- printf("Au1000: 48MHz OHCI workaround enabled\n");
- break;
-
- default: /* HC and newer */
- /* FREQ2 = aux/2 = 48 MHz */
- sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
- au_writel(sys_freqctrl, SYS_FREQCTRL0);
- break;
- }
-
- /*
- * Route 48MHz FREQ2 into USB Host and/or Device
- */
- sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
- au_writel(sys_clksrc, SYS_CLKSRC);
-
- /* configure pins GPIO[14:9] as GPIO */
- pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
-
- au_writel(pin_func, SYS_PINFUNC);
- au_writel(0x2800, SYS_TRIOUTCLR);
- au_writel(0x0030, SYS_OUTPUTCLR);
-
- dbg("OHCI board setup complete\n");
-
- /* enable host controller */
- au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
- udelay(1000);
- au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
- udelay(1000);
-
- /* wait for reset complete (read register twice; see au1500 errata) */
- while (au_readl(USB_HOST_CONFIG),
- !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
- udelay(1000);
-
- dbg("OHCI clock running\n");
-
- memset (&gohci, 0, sizeof (ohci_t));
- memset (&urb_priv, 0, sizeof (urb_priv_t));
-
- /* align the storage */
- if ((__u32)&ghcca[0] & 0xff) {
- err("HCCA not aligned!!");
- return -1;
- }
- phcca = &ghcca[0];
- info("aligned ghcca %p", phcca);
- memset(&ohci_dev, 0, sizeof(struct ohci_device));
- if ((__u32)&ohci_dev.ed[0] & 0x7) {
- err("EDs not aligned!!");
- return -1;
- }
- memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
- if ((__u32)gtd & 0x7) {
- err("TDs not aligned!!");
- return -1;
- }
- ptd = gtd;
- gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
-
- gohci.disabled = 1;
- gohci.sleeping = 0;
- gohci.irq = -1;
- gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
-
- gohci.flags = 0;
- gohci.slot_name = "au1x00";
-
- dbg("OHCI revision: 0x%08x\n"
- " RH: a: 0x%08x b: 0x%08x\n",
- readl(&gohci.regs->revision),
- readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
-
- if (hc_reset (&gohci) < 0)
- goto errout;
-
- /* FIXME this is a second HC reset; why?? */
- writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
- mdelay (10);
-
- if (hc_start (&gohci) < 0)
- goto errout;
-
-#ifdef DEBUG
- ohci_dump (&gohci, 1);
-#else
- mdelay(1);
-#endif
- ohci_inited = 1;
- return 0;
-
- errout:
- err("OHCI initialization error\n");
- hc_release_ohci (&gohci);
- /* Initialization failed */
- au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- return -1;
-}
-
-int usb_lowlevel_stop(int index)
-{
- /* this gets called really early - before the controller has */
- /* even been initialized! */
- if (!ohci_inited)
- return 0;
- /* TODO release any interrupts, etc. */
- /* call hc_release_ohci() here ? */
- hc_reset (&gohci);
- /* may not want to do this */
- /* Disable clock */
- au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
- return 0;
-}
-
-#endif /* CONFIG_USB_OHCI */
deleted file mode 100644
@@ -1,416 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
- /* No Error */ 0,
- /* CRC Error */ USB_ST_CRC_ERR,
- /* Bit Stuff */ USB_ST_BIT_ERR,
- /* Data Togg */ USB_ST_CRC_ERR,
- /* Stall */ USB_ST_STALLED,
- /* DevNotResp */ -1,
- /* PIDCheck */ USB_ST_BIT_ERR,
- /* UnExpPID */ USB_ST_BIT_ERR,
- /* DataOver */ USB_ST_BUF_ERR,
- /* DataUnder */ USB_ST_BUF_ERR,
- /* reservd */ -1,
- /* reservd */ -1,
- /* BufferOver */ USB_ST_BUF_ERR,
- /* BuffUnder */ USB_ST_BUF_ERR,
- /* Not Access */ -1,
- /* Not Access */ -1
-};
-
-/* ED States */
-
-#define ED_NEW 0x00
-#define ED_UNLINK 0x01
-#define ED_OPER 0x02
-#define ED_DEL 0x04
-#define ED_URB_DEL 0x08
-
-/* usb_ohci_ed */
-struct ed {
- __u32 hwINFO;
- __u32 hwTailP;
- __u32 hwHeadP;
- __u32 hwNextED;
-
- struct ed *ed_prev;
- __u8 int_period;
- __u8 int_branch;
- __u8 int_load;
- __u8 int_interval;
- __u8 state;
- __u8 type;
- __u16 last_iso;
- struct ed *ed_rm_list;
-
- struct usb_device *usb_dev;
- __u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
-
-/* TD info field */
-#define TD_CC 0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
-#define TD_EC 0x0C000000
-#define TD_T 0x03000000
-#define TD_T_DATA0 0x02000000
-#define TD_T_DATA1 0x03000000
-#define TD_T_TOGGLE 0x00000000
-#define TD_R 0x00040000
-#define TD_DI 0x00E00000
-#define TD_DI_SET(X) (((X) & 0x07)<< 21)
-#define TD_DP 0x00180000
-#define TD_DP_SETUP 0x00000000
-#define TD_DP_IN 0x00100000
-#define TD_DP_OUT 0x00080000
-
-#define TD_ISO 0x00010000
-#define TD_DEL 0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR 0x00
-#define TD_CC_CRC 0x01
-#define TD_CC_BITSTUFFING 0x02
-#define TD_CC_DATATOGGLEM 0x03
-#define TD_CC_STALL 0x04
-#define TD_DEVNOTRESP 0x05
-#define TD_PIDCHECKFAIL 0x06
-#define TD_UNEXPECTEDPID 0x07
-#define TD_DATAOVERRUN 0x08
-#define TD_DATAUNDERRUN 0x09
-#define TD_BUFFEROVERRUN 0x0C
-#define TD_BUFFERUNDERRUN 0x0D
-#define TD_NOTACCESSED 0x0F
-
-
-#define MAXPSW 1
-
-struct td {
- __u32 hwINFO;
- __u32 hwCBP; /* Current Buffer Pointer */
- __u32 hwNextTD; /* Next TD Pointer */
- __u32 hwBE; /* Memory Buffer End Pointer */
-
- __u16 hwPSW[MAXPSW];
- __u8 unused;
- __u8 index;
- struct ed *ed;
- struct td *next_dl_td;
- struct usb_device *usb_dev;
- int transfer_len;
- __u32 data;
-
- __u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
-
-#define OHCI_ED_SKIP (1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of. It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32 /* part of the OHCI standard */
-struct ohci_hcca {
- __u32 int_table[NUM_INTS]; /* Interrupt ED table */
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
- __u32 done_head; /* info returned for an interrupt */
- u8 reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region. This is Memory Mapped I/O. You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
- /* control and status registers */
- __u32 revision;
- __u32 control;
- __u32 cmdstatus;
- __u32 intrstatus;
- __u32 intrenable;
- __u32 intrdisable;
- /* memory pointers */
- __u32 hcca;
- __u32 ed_periodcurrent;
- __u32 ed_controlhead;
- __u32 ed_controlcurrent;
- __u32 ed_bulkhead;
- __u32 ed_bulkcurrent;
- __u32 donehead;
- /* frame counters */
- __u32 fminterval;
- __u32 fmremaining;
- __u32 fmnumber;
- __u32 periodicstart;
- __u32 lsthresh;
- /* Root hub ports */
- struct ohci_roothub_regs {
- __u32 a;
- __u32 b;
- __u32 status;
- __u32 portstatus[MAX_ROOT_PORTS];
- } roothub;
-} __attribute__((aligned(32)));
-
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
-#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
-#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
-#define OHCI_CTRL_CLE (1 << 4) /* control list enable */
-#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
-#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
-#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
-#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
-#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-# define OHCI_USB_RESET (0 << 6)
-# define OHCI_USB_RESUME (1 << 6)
-# define OHCI_USB_OPER (2 << 6)
-# define OHCI_USB_SUSPEND (3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR (1 << 0) /* host controller reset */
-#define OHCI_CLF (1 << 1) /* control list filled */
-#define OHCI_BLF (1 << 2) /* bulk list filled */
-#define OHCI_OCR (1 << 3) /* ownership change request */
-#define OHCI_SOC (3 << 16) /* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
-#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
-#define OHCI_INTR_SF (1 << 2) /* start frame */
-#define OHCI_INTR_RD (1 << 3) /* resume detect */
-#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
-#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
-#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
-#define OHCI_INTR_OC (1 << 30) /* ownership change */
-#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
-
-/* Virtual Root HUB */
-struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- void *dev; /* was urb */
- void *int_addr;
- int send;
- int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE 0x01
-#define RH_ENDPOINT 0x02
-#define RH_OTHER 0x03
-
-#define RH_CLASS 0x20
-#define RH_VENDOR 0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS 0x0080
-#define RH_CLEAR_FEATURE 0x0100
-#define RH_SET_FEATURE 0x0300
-#define RH_SET_ADDRESS 0x0500
-#define RH_GET_DESCRIPTOR 0x0680
-#define RH_SET_DESCRIPTOR 0x0700
-#define RH_GET_CONFIGURATION 0x0880
-#define RH_SET_CONFIGURATION 0x0900
-#define RH_GET_STATE 0x0280
-#define RH_GET_INTERFACE 0x0A80
-#define RH_SET_INTERFACE 0x0B00
-#define RH_SYNC_FRAME 0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP 0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION 0x00
-#define RH_PORT_ENABLE 0x01
-#define RH_PORT_SUSPEND 0x02
-#define RH_PORT_OVER_CURRENT 0x03
-#define RH_PORT_RESET 0x04
-#define RH_PORT_POWER 0x08
-#define RH_PORT_LOW_SPEED 0x09
-
-#define RH_C_PORT_CONNECTION 0x10
-#define RH_C_PORT_ENABLE 0x11
-#define RH_C_PORT_SUSPEND 0x12
-#define RH_C_PORT_OVER_CURRENT 0x13
-#define RH_C_PORT_RESET 0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER 0x00
-#define RH_C_HUB_OVER_CURRENT 0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL 0x01
-
-#define RH_ACK 0x01
-#define RH_REQ_ERR -1
-#define RH_NACK 0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS 0x00000001 /* current connect status */
-#define RH_PS_PES 0x00000002 /* port enable status*/
-#define RH_PS_PSS 0x00000004 /* port suspend status */
-#define RH_PS_POCI 0x00000008 /* port over current indicator */
-#define RH_PS_PRS 0x00000010 /* port reset status */
-#define RH_PS_PPS 0x00000100 /* port power status */
-#define RH_PS_LSDA 0x00000200 /* low speed device attached */
-#define RH_PS_CSC 0x00010000 /* connect status change */
-#define RH_PS_PESC 0x00020000 /* port enable status change */
-#define RH_PS_PSSC 0x00040000 /* port suspend status change */
-#define RH_PS_OCIC 0x00080000 /* over current indicator change */
-#define RH_PS_PRSC 0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS 0x00000001 /* local power status */
-#define RH_HS_OCI 0x00000002 /* over current indicator */
-#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC 0x00010000 /* local power status change */
-#define RH_HS_OCIC 0x00020000 /* over current indicator change */
-#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR 0x0000ffff /* device removable flags */
-#define RH_B_PPCM 0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
-#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-typedef struct
-{
- ed_t *ed;
- __u16 length; /* number of tds associated with this request */
- __u16 td_cnt; /* number of tds already serviced */
- int state;
- unsigned long pipe;
- int actual_length;
- td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-typedef struct ohci {
- struct ohci_hcca *hcca; /* hcca */
- /*dma_addr_t hcca_dma;*/
-
- int irq;
- int disabled; /* e.g. got a UE, we're hung */
- int sleeping;
- unsigned long flags; /* for HC bugs */
-
- struct ohci_regs *regs; /* OHCI controller's memory */
-
- ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
- ed_t *ed_bulktail; /* last endpoint of bulk list */
- ed_t *ed_controltail; /* last endpoint of control list */
- int intrstatus;
- __u32 hc_control; /* copy of the hc control reg */
- struct usb_device *dev[32];
- struct virt_root_hub rh;
-
- const char *slot_name;
-} ohci_t;
-
-#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
-
-struct ohci_device {
- ed_t ed[NUM_EDS];
- int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(ohci_t * ohci, ed_t * ed);
-static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-td_t gtd[NUM_TD+1];
-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *
-td_alloc (struct usb_device *usb_dev)
-{
- int i;
- struct td *td;
-
- td = NULL;
- for (i = 0; i < NUM_TD; i++) {
- if (ptd[i].usb_dev == NULL) {
- td = &ptd[i];
- td->usb_dev = usb_dev;
- break;
- }
- }
- return td;
-}
-
-static inline void
-ed_free (struct ed *ed)
-{
- ed->usb_dev = NULL;
-}
deleted file mode 100644
@@ -1,1040 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2000,2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- * ppopov@mvista.com or source@mvista.com
- */
-
- /*
- * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
- */
-
-#ifndef _AU1X00_H_
-#define _AU1X00_H_
-
-#ifndef __ASSEMBLY__
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
- __asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
- __asm__ volatile ("sync");
- udelay(us);
-}
-
-void static inline au_writeb(u8 val, int reg)
-{
- *(volatile u8 *)(reg) = val;
-}
-
-void static inline au_writew(u16 val, int reg)
-{
- *(volatile u16 *)(reg) = val;
-}
-
-void static inline au_writel(u32 val, int reg)
-{
- *(volatile u32 *)(reg) = val;
-}
-
-static inline u8 au_readb(unsigned long port)
-{
- return (*(volatile u8 *)port);
-}
-
-static inline u16 au_readw(unsigned long port)
-{
- return (*(volatile u16 *)port);
-}
-
-static inline u32 au_readl(unsigned long port)
-{
- return (*(volatile u32 *)port);
-}
-
-/* These next three functions should be a generic part of the MIPS
- * kernel (with the 'au_' removed from the name) and selected for
- * processors that support the instructions.
- * Taken from PPC tree. -- Dan
- */
-/* Return the bit position of the most significant 1 bit in a word */
-static __inline__ int __ilog2(unsigned int x)
-{
- int lz;
-
- asm volatile (
- ".set\tnoreorder\n\t"
- ".set\tnoat\n\t"
- ".set\tmips32\n\t"
- "clz\t%0,%1\n\t"
- ".set\tmips0\n\t"
- ".set\tat\n\t"
- ".set\treorder"
- : "=r" (lz)
- : "r" (x));
-
- return 31 - lz;
-}
-
-static __inline__ int au_ffz(unsigned int x)
-{
- if ((x = ~x) == 0)
- return 32;
- return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
- return __ilog2(x & -x) + 1;
-}
-
-#define gpio_set(Value) outl(Value, SYS_OUTPUTSET)
-#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR)
-#define gpio_read() inl(SYS_PINSTATERD)
-#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
-
-#endif /* !ASSEMBLY */
-
-#ifdef CONFIG_PM
-/* no CP0 timer irq */
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
-#else
-#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
-#endif
-
-#define CP0_IWATCHLO $18,1
-#define CP0_DEBUG $23
-
-/* SDRAM Controller */
-#define MEM_SDMODE0 0xB4000000
-#define MEM_SDMODE1 0xB4000004
-#define MEM_SDMODE2 0xB4000008
-
-#define MEM_SDADDR0 0xB400000C
-#define MEM_SDADDR1 0xB4000010
-#define MEM_SDADDR2 0xB4000014
-
-#define MEM_SDREFCFG 0xB4000018
-#define MEM_SDPRECMD 0xB400001C
-#define MEM_SDAUTOREF 0xB4000020
-
-#define MEM_SDWRMD0 0xB4000024
-#define MEM_SDWRMD1 0xB4000028
-#define MEM_SDWRMD2 0xB400002C
-
-#define MEM_SDSLEEP 0xB4000030
-#define MEM_SDSMCKE 0xB4000034
-
-/* Static Bus Controller */
-#define MEM_STCFG0 0xB4001000
-#define MEM_STTIME0 0xB4001004
-#define MEM_STADDR0 0xB4001008
-
-#define MEM_STCFG1 0xB4001010
-#define MEM_STTIME1 0xB4001014
-#define MEM_STADDR1 0xB4001018
-
-#define MEM_STCFG2 0xB4001020
-#define MEM_STTIME2 0xB4001024
-#define MEM_STADDR2 0xB4001028
-
-#define MEM_STCFG3 0xB4001030
-#define MEM_STTIME3 0xB4001034
-#define MEM_STADDR3 0xB4001038
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD 0xB0400040
-#define IC0_CFG0SET 0xB0400040
-#define IC0_CFG0CLR 0xB0400044
-
-#define IC0_CFG1RD 0xB0400048
-#define IC0_CFG1SET 0xB0400048
-#define IC0_CFG1CLR 0xB040004C
-
-#define IC0_CFG2RD 0xB0400050
-#define IC0_CFG2SET 0xB0400050
-#define IC0_CFG2CLR 0xB0400054
-
-#define IC0_REQ0INT 0xB0400054
-#define IC0_SRCRD 0xB0400058
-#define IC0_SRCSET 0xB0400058
-#define IC0_SRCCLR 0xB040005C
-#define IC0_REQ1INT 0xB040005C
-
-#define IC0_ASSIGNRD 0xB0400060
-#define IC0_ASSIGNSET 0xB0400060
-#define IC0_ASSIGNCLR 0xB0400064
-
-#define IC0_WAKERD 0xB0400068
-#define IC0_WAKESET 0xB0400068
-#define IC0_WAKECLR 0xB040006C
-
-#define IC0_MASKRD 0xB0400070
-#define IC0_MASKSET 0xB0400070
-#define IC0_MASKCLR 0xB0400074
-
-#define IC0_RISINGRD 0xB0400078
-#define IC0_RISINGCLR 0xB0400078
-#define IC0_FALLINGRD 0xB040007C
-#define IC0_FALLINGCLR 0xB040007C
-
-#define IC0_TESTBIT 0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD 0xB1800040
-#define IC1_CFG0SET 0xB1800040
-#define IC1_CFG0CLR 0xB1800044
-
-#define IC1_CFG1RD 0xB1800048
-#define IC1_CFG1SET 0xB1800048
-#define IC1_CFG1CLR 0xB180004C
-
-#define IC1_CFG2RD 0xB1800050
-#define IC1_CFG2SET 0xB1800050
-#define IC1_CFG2CLR 0xB1800054
-
-#define IC1_REQ0INT 0xB1800054
-#define IC1_SRCRD 0xB1800058
-#define IC1_SRCSET 0xB1800058
-#define IC1_SRCCLR 0xB180005C
-#define IC1_REQ1INT 0xB180005C
-
-#define IC1_ASSIGNRD 0xB1800060
-#define IC1_ASSIGNSET 0xB1800060
-#define IC1_ASSIGNCLR 0xB1800064
-
-#define IC1_WAKERD 0xB1800068
-#define IC1_WAKESET 0xB1800068
-#define IC1_WAKECLR 0xB180006C
-
-#define IC1_MASKRD 0xB1800070
-#define IC1_MASKSET 0xB1800070
-#define IC1_MASKCLR 0xB1800074
-
-#define IC1_RISINGRD 0xB1800078
-#define IC1_RISINGCLR 0xB1800078
-#define IC1_FALLINGRD 0xB180007C
-#define IC1_FALLINGCLR 0xB180007C
-
-#define IC1_TESTBIT 0xB1800080
-
-/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED 0
-#define INTC_INT_RISE_EDGE 0x1
-#define INTC_INT_FALL_EDGE 0x2
-#define INTC_INT_RISE_AND_FALL_EDGE 0x3
-#define INTC_INT_HIGH_LEVEL 0x5
-#define INTC_INT_LOW_LEVEL 0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
-
-/* Interrupt Numbers */
-#define AU1X00_UART0_INT 0
-#define AU1000_UART1_INT 1 /* au1000 */
-#define AU1000_UART2_INT 2 /* au1000 */
-
-#define AU1500_PCI_INTA 1 /* au1500 */
-#define AU1500_PCI_INTB 2 /* au1500 */
-
-#define AU1X00_UART3_INT 3
-
-#define AU1000_SSI0_INT 4 /* au1000 */
-#define AU1000_SSI1_INT 5 /* au1000 */
-
-#define AU1500_PCI_INTC 4 /* au1500 */
-#define AU1500_PCI_INTD 5 /* au1500 */
-
-#define AU1X00_DMA_INT_BASE 6
-#define AU1X00_TOY_INT 14
-#define AU1X00_TOY_MATCH0_INT 15
-#define AU1X00_TOY_MATCH1_INT 16
-#define AU1X00_TOY_MATCH2_INT 17
-#define AU1X00_RTC_INT 18
-#define AU1X00_RTC_MATCH0_INT 19
-#define AU1X00_RTC_MATCH1_INT 20
-#define AU1X00_RTC_MATCH2_INT 21
-#define AU1000_IRDA_TX_INT 22 /* au1000 */
-#define AU1000_IRDA_RX_INT 23 /* au1000 */
-#define AU1X00_USB_DEV_REQ_INT 24
-#define AU1X00_USB_DEV_SUS_INT 25
-#define AU1X00_USB_HOST_INT 26
-#define AU1X00_ACSYNC_INT 27
-#define AU1X00_MAC0_DMA_INT 28
-#define AU1X00_MAC1_DMA_INT 29
-#define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT
-#define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT
-#define AU1000_I2S_UO_INT 30 /* au1000 */
-#define AU1X00_AC97C_INT 31
-#define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT
-#define AU1X00_GPIO_0 32
-#define AU1X00_GPIO_1 33
-#define AU1X00_GPIO_2 34
-#define AU1X00_GPIO_3 35
-#define AU1X00_GPIO_4 36
-#define AU1X00_GPIO_5 37
-#define AU1X00_GPIO_6 38
-#define AU1X00_GPIO_7 39
-#define AU1X00_GPIO_8 40
-#define AU1X00_GPIO_9 41
-#define AU1X00_GPIO_10 42
-#define AU1X00_GPIO_11 43
-#define AU1X00_GPIO_12 44
-#define AU1X00_GPIO_13 45
-#define AU1X00_GPIO_14 46
-#define AU1X00_GPIO_15 47
-
-/* Au1000 only */
-#define AU1000_GPIO_16 48
-#define AU1000_GPIO_17 49
-#define AU1000_GPIO_18 50
-#define AU1000_GPIO_19 51
-#define AU1000_GPIO_20 52
-#define AU1000_GPIO_21 53
-#define AU1000_GPIO_22 54
-#define AU1000_GPIO_23 55
-#define AU1000_GPIO_24 56
-#define AU1000_GPIO_25 57
-#define AU1000_GPIO_26 58
-#define AU1000_GPIO_27 59
-#define AU1000_GPIO_28 60
-#define AU1000_GPIO_29 61
-#define AU1000_GPIO_30 62
-#define AU1000_GPIO_31 63
-
-/* Au1500 only */
-#define AU1500_GPIO_200 48
-#define AU1500_GPIO_201 49
-#define AU1500_GPIO_202 50
-#define AU1500_GPIO_203 51
-#define AU1500_GPIO_20 52
-#define AU1500_GPIO_204 53
-#define AU1500_GPIO_205 54
-#define AU1500_GPIO_23 55
-#define AU1500_GPIO_24 56
-#define AU1500_GPIO_25 57
-#define AU1500_GPIO_26 58
-#define AU1500_GPIO_27 59
-#define AU1500_GPIO_28 60
-#define AU1500_GPIO_206 61
-#define AU1500_GPIO_207 62
-#define AU1500_GPIO_208_215 63
-
-#define AU1X00_MAX_INTR 63
-
-#define AU1100_SD 2
-#define AU1100_GPIO_208_215 29
-/* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
-
-/* Programmable Counters 0 and 1 */
-#define SYS_BASE 0xB1900000
-#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
-#define SYS_CNTRL_E1S (1<<23)
-#define SYS_CNTRL_T1S (1<<20)
-#define SYS_CNTRL_M21 (1<<19)
-#define SYS_CNTRL_M11 (1<<18)
-#define SYS_CNTRL_M01 (1<<17)
-#define SYS_CNTRL_C1S (1<<16)
-#define SYS_CNTRL_BP (1<<14)
-#define SYS_CNTRL_EN1 (1<<13)
-#define SYS_CNTRL_BT1 (1<<12)
-#define SYS_CNTRL_EN0 (1<<11)
-#define SYS_CNTRL_BT0 (1<<10)
-#define SYS_CNTRL_E0 (1<<8)
-#define SYS_CNTRL_E0S (1<<7)
-#define SYS_CNTRL_32S (1<<5)
-#define SYS_CNTRL_T0S (1<<4)
-#define SYS_CNTRL_M20 (1<<3)
-#define SYS_CNTRL_M10 (1<<2)
-#define SYS_CNTRL_M00 (1<<1)
-#define SYS_CNTRL_C0S (1<<0)
-
-/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM (SYS_BASE + 0)
-#define SYS_TOYWRITE (SYS_BASE + 4)
-#define SYS_TOYMATCH0 (SYS_BASE + 8)
-#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
-#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
-#define SYS_TOYREAD (SYS_BASE + 0x40)
-
-/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM (SYS_BASE + 0x44)
-#define SYS_RTCWRITE (SYS_BASE + 0x48)
-#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
-#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
-#define SYS_RTCREAD (SYS_BASE + 0x58)
-
-/* I2S Controller */
-#define I2S_DATA 0xB1000000
-#define I2S_DATA_MASK (0xffffff)
-#define I2S_CONFIG 0xB1000004
-#define I2S_CONFIG_XU (1<<25)
-#define I2S_CONFIG_XO (1<<24)
-#define I2S_CONFIG_RU (1<<23)
-#define I2S_CONFIG_RO (1<<22)
-#define I2S_CONFIG_TR (1<<21)
-#define I2S_CONFIG_TE (1<<20)
-#define I2S_CONFIG_TF (1<<19)
-#define I2S_CONFIG_RR (1<<18)
-#define I2S_CONFIG_RE (1<<17)
-#define I2S_CONFIG_RF (1<<16)
-#define I2S_CONFIG_PD (1<<11)
-#define I2S_CONFIG_LB (1<<10)
-#define I2S_CONFIG_IC (1<<9)
-#define I2S_CONFIG_FM_BIT 7
-#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
-#define I2S_CONFIG_TN (1<<6)
-#define I2S_CONFIG_RN (1<<5)
-#define I2S_CONFIG_SZ_BIT 0
-#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL 0xB1000008
-#define I2S_CONTROL_D (1<<1)
-#define I2S_CONTROL_CE (1<<0)
-
-/* USB Host Controller */
-/* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
-#define USB_OHCI_BASE 0x10100000
-#define USB_OHCI_LEN 0x00100000
-#define USB_HOST_CONFIG 0xB017fffc
-
-/* USB Device Controller */
-#define USBD_EP0RD 0xB0200000
-#define USBD_EP0WR 0xB0200004
-#define USBD_EP2WR 0xB0200008
-#define USBD_EP3WR 0xB020000C
-#define USBD_EP4RD 0xB0200010
-#define USBD_EP5RD 0xB0200014
-#define USBD_INTEN 0xB0200018
-#define USBD_INTSTAT 0xB020001C
-#define USBDEV_INT_SOF (1<<12)
-#define USBDEV_INT_HF_BIT 6
-#define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
-#define USBDEV_INT_CMPLT_BIT 0
-#define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG 0xB0200020
-#define USBD_EP0CS 0xB0200024
-#define USBD_EP2CS 0xB0200028
-#define USBD_EP3CS 0xB020002C
-#define USBD_EP4CS 0xB0200030
-#define USBD_EP5CS 0xB0200034
-#define USBDEV_CS_SU (1<<14)
-#define USBDEV_CS_NAK (1<<13)
-#define USBDEV_CS_ACK (1<<12)
-#define USBDEV_CS_BUSY (1<<11)
-#define USBDEV_CS_TSIZE_BIT 1
-#define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
-#define USBDEV_CS_STALL (1<<0)
-#define USBD_EP0RDSTAT 0xB0200040
-#define USBD_EP0WRSTAT 0xB0200044
-#define USBD_EP2WRSTAT 0xB0200048
-#define USBD_EP3WRSTAT 0xB020004C
-#define USBD_EP4RDSTAT 0xB0200050
-#define USBD_EP5RDSTAT 0xB0200054
-#define USBDEV_FSTAT_FLUSH (1<<6)
-#define USBDEV_FSTAT_UF (1<<5)
-#define USBDEV_FSTAT_OF (1<<4)
-#define USBDEV_FSTAT_FCNT_BIT 0
-#define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE 0xB0200058
-#define USBDEV_ENABLE (1<<1)
-#define USBDEV_CE (1<<0)
-
-/* Ethernet Controllers */
-#define AU1000_ETH0_BASE 0xB0500000
-#define AU1000_ETH1_BASE 0xB0510000
-#define AU1500_ETH0_BASE 0xB1500000
-#define AU1500_ETH1_BASE 0xB1510000
-#define AU1100_ETH0_BASE 0xB0500000
-
-/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL 0x0
-#define MAC_RX_ENABLE (1<<2)
-#define MAC_TX_ENABLE (1<<3)
-#define MAC_DEF_CHECK (1<<5)
-#define MAC_SET_BL(X) (((X)&0x3)<<6)
-#define MAC_AUTO_PAD (1<<8)
-#define MAC_DISABLE_RETRY (1<<10)
-#define MAC_DISABLE_BCAST (1<<11)
-#define MAC_LATE_COL (1<<12)
-#define MAC_HASH_MODE (1<<13)
-#define MAC_HASH_ONLY (1<<15)
-#define MAC_PASS_ALL (1<<16)
-#define MAC_INVERSE_FILTER (1<<17)
-#define MAC_PROMISCUOUS (1<<18)
-#define MAC_PASS_ALL_MULTI (1<<19)
-#define MAC_FULL_DUPLEX (1<<20)
-#define MAC_NORMAL_MODE 0
-#define MAC_INT_LOOPBACK (1<<21)
-#define MAC_EXT_LOOPBACK (1<<22)
-#define MAC_DISABLE_RX_OWN (1<<23)
-#define MAC_BIG_ENDIAN (1<<30)
-#define MAC_RX_ALL (1<<31)
-#define MAC_ADDRESS_HIGH 0x4
-#define MAC_ADDRESS_LOW 0x8
-#define MAC_MCAST_HIGH 0xC
-#define MAC_MCAST_LOW 0x10
-#define MAC_MII_CNTRL 0x14
-#define MAC_MII_BUSY (1<<0)
-#define MAC_MII_READ 0
-#define MAC_MII_WRITE (1<<1)
-#define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
-#define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
-#define MAC_MII_DATA 0x18
-#define MAC_FLOW_CNTRL 0x1C
-#define MAC_FLOW_CNTRL_BUSY (1<<0)
-#define MAC_FLOW_CNTRL_ENABLE (1<<1)
-#define MAC_PASS_CONTROL (1<<2)
-#define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
-#define MAC_VLAN1_TAG 0x20
-#define MAC_VLAN2_TAG 0x24
-
-/* Ethernet Controller Enable */
-#define AU1000_MAC0_ENABLE 0xB0520000
-#define AU1000_MAC1_ENABLE 0xB0520004
-#define AU1500_MAC0_ENABLE 0xB1520000
-#define AU1500_MAC1_ENABLE 0xB1520004
-#define AU1100_MAC0_ENABLE 0xB0520000
-
-#define MAC_EN_CLOCK_ENABLE (1<<0)
-#define MAC_EN_RESET0 (1<<1)
-#define MAC_EN_TOSS (0<<2)
-#define MAC_EN_CACHEABLE (1<<3)
-#define MAC_EN_RESET1 (1<<4)
-#define MAC_EN_RESET2 (1<<5)
-#define MAC_DMA_RESET (1<<6)
-
-/* Ethernet Controller DMA Channels */
-
-#define MAC0_TX_DMA_ADDR 0xB4004000
-#define MAC1_TX_DMA_ADDR 0xB4004200
-/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS 0x0
-#define TX_FRAME_ABORTED (1<<0)
-#define TX_JAB_TIMEOUT (1<<1)
-#define TX_NO_CARRIER (1<<2)
-#define TX_LOSS_CARRIER (1<<3)
-#define TX_EXC_DEF (1<<4)
-#define TX_LATE_COLL_ABORT (1<<5)
-#define TX_EXC_COLL (1<<6)
-#define TX_UNDERRUN (1<<7)
-#define TX_DEFERRED (1<<8)
-#define TX_LATE_COLL (1<<9)
-#define TX_COLL_CNT_MASK (0xF<<10)
-#define TX_PKT_RETRY (1<<31)
-#define MAC_TX_BUFF0_ADDR 0x4
-#define TX_DMA_ENABLE (1<<0)
-#define TX_T_DONE (1<<1)
-#define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-#define MAC_TX_BUFF0_LEN 0x8
-#define MAC_TX_BUFF1_STATUS 0x10
-#define MAC_TX_BUFF1_ADDR 0x14
-#define MAC_TX_BUFF1_LEN 0x18
-#define MAC_TX_BUFF2_STATUS 0x20
-#define MAC_TX_BUFF2_ADDR 0x24
-#define MAC_TX_BUFF2_LEN 0x28
-#define MAC_TX_BUFF3_STATUS 0x30
-#define MAC_TX_BUFF3_ADDR 0x34
-#define MAC_TX_BUFF3_LEN 0x38
-
-#define MAC0_RX_DMA_ADDR 0xB4004100
-#define MAC1_RX_DMA_ADDR 0xB4004300
-/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS 0x0
-#define RX_FRAME_LEN_MASK 0x3fff
-#define RX_WDOG_TIMER (1<<14)
-#define RX_RUNT (1<<15)
-#define RX_OVERLEN (1<<16)
-#define RX_COLL (1<<17)
-#define RX_ETHER (1<<18)
-#define RX_MII_ERROR (1<<19)
-#define RX_DRIBBLING (1<<20)
-#define RX_CRC_ERROR (1<<21)
-#define RX_VLAN1 (1<<22)
-#define RX_VLAN2 (1<<23)
-#define RX_LEN_ERROR (1<<24)
-#define RX_CNTRL_FRAME (1<<25)
-#define RX_U_CNTRL_FRAME (1<<26)
-#define RX_MCAST_FRAME (1<<27)
-#define RX_BCAST_FRAME (1<<28)
-#define RX_FILTER_FAIL (1<<29)
-#define RX_PACKET_FILTER (1<<30)
-#define RX_MISSED_FRAME (1<<31)
-
-#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
- RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
- RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR 0x4
-#define RX_DMA_ENABLE (1<<0)
-#define RX_T_DONE (1<<1)
-#define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
-#define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
-#define MAC_RX_BUFF1_STATUS 0x10
-#define MAC_RX_BUFF1_ADDR 0x14
-#define MAC_RX_BUFF2_STATUS 0x20
-#define MAC_RX_BUFF2_ADDR 0x24
-#define MAC_RX_BUFF3_STATUS 0x30
-#define MAC_RX_BUFF3_ADDR 0x34
-
-
-/* UARTS 0-3 */
-#define UART0_ADDR 0xB1100000
-#define UART1_ADDR 0xB1200000
-#define UART2_ADDR 0xB1300000
-#define UART3_ADDR 0xB1400000
-#define UART_BASE UART0_ADDR
-#define UART_DEBUG_BASE UART2_ADDR
-
-#define UART_RX 0 /* Receive buffer */
-#define UART_TX 4 /* Transmit buffer */
-#define UART_IER 8 /* Interrupt Enable Register */
-#define UART_IIR 0xC /* Interrupt ID Register */
-#define UART_FCR 0x10 /* FIFO Control Register */
-#define UART_LCR 0x14 /* Line Control Register */
-#define UART_MCR 0x18 /* Modem Control Register */
-#define UART_LSR 0x1C /* Line Status Register */
-#define UART_MSR 0x20 /* Modem Status Register */
-#define UART_CLK 0x28 /* Baud Rate Clock Divider */
-#define UART_ENABLE 0x100 /* Uart enable */
-
-#define UART_EN_CE 1 /* Clock enable */
-#define UART_EN_E 2 /* Enable */
-
-#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC 0x40 /* Set break control */
-#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
-#define UART_LCR_EPAR 0x10 /* Even parity select */
-#define UART_LCR_PARITY 0x08 /* Parity Enable */
-#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT 0x40 /* Transmitter empty */
-#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
-#define UART_LSR_BI 0x10 /* Break interrupt indicator */
-#define UART_LSR_FE 0x08 /* Frame error indicator */
-#define UART_LSR_PE 0x04 /* Parity error indicator */
-#define UART_LSR_OE 0x02 /* Overrun error indicator */
-#define UART_LSR_DR 0x01 /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-#define UART_MCR_OUT2 0x08 /* Out2 complement */
-#define UART_MCR_OUT1 0x04 /* Out1 complement */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
-#define UART_MSR_RI 0x40 /* Ring Indicator */
-#define UART_MSR_DSR 0x20 /* Data Set Ready */
-#define UART_MSR_CTS 0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
-
-/* SSIO */
-#define SSI0_STATUS 0xB1600000
-#define SSI_STATUS_BF (1<<4)
-#define SSI_STATUS_OF (1<<3)
-#define SSI_STATUS_UF (1<<2)
-#define SSI_STATUS_D (1<<1)
-#define SSI_STATUS_B (1<<0)
-#define SSI0_INT 0xB1600004
-#define SSI_INT_OI (1<<3)
-#define SSI_INT_UI (1<<2)
-#define SSI_INT_DI (1<<1)
-#define SSI0_INT_ENABLE 0xB1600008
-#define SSI_INTE_OIE (1<<3)
-#define SSI_INTE_UIE (1<<2)
-#define SSI_INTE_DIE (1<<1)
-#define SSI0_CONFIG 0xB1600020
-#define SSI_CONFIG_AO (1<<24)
-#define SSI_CONFIG_DO (1<<23)
-#define SSI_CONFIG_ALEN_BIT 20
-#define SSI_CONFIG_ALEN_MASK (0x7<<20)
-#define SSI_CONFIG_DLEN_BIT 16
-#define SSI_CONFIG_DLEN_MASK (0x7<<16)
-#define SSI_CONFIG_DD (1<<11)
-#define SSI_CONFIG_AD (1<<10)
-#define SSI_CONFIG_BM_BIT 8
-#define SSI_CONFIG_BM_MASK (0x3<<8)
-#define SSI_CONFIG_CE (1<<7)
-#define SSI_CONFIG_DP (1<<6)
-#define SSI_CONFIG_DL (1<<5)
-#define SSI_CONFIG_EP (1<<4)
-#define SSI0_ADATA 0xB1600024
-#define SSI_AD_D (1<<24)
-#define SSI_AD_ADDR_BIT 16
-#define SSI_AD_ADDR_MASK (0xff<<16)
-#define SSI_AD_DATA_BIT 0
-#define SSI_AD_DATA_MASK (0xfff<<0)
-#define SSI0_CLKDIV 0xB1600028
-#define SSI0_CONTROL 0xB1600100
-#define SSI_CONTROL_CD (1<<1)
-#define SSI_CONTROL_E (1<<0)
-
-/* SSI1 */
-#define SSI1_STATUS 0xB1680000
-#define SSI1_INT 0xB1680004
-#define SSI1_INT_ENABLE 0xB1680008
-#define SSI1_CONFIG 0xB1680020
-#define SSI1_ADATA 0xB1680024
-#define SSI1_CLKDIV 0xB1680028
-#define SSI1_ENABLE 0xB1680100
-
-/*
- * Register content definitions
- */
-#define SSI_STATUS_BF (1<<4)
-#define SSI_STATUS_OF (1<<3)
-#define SSI_STATUS_UF (1<<2)
-#define SSI_STATUS_D (1<<1)
-#define SSI_STATUS_B (1<<0)
-
-/* SSI_INT */
-#define SSI_INT_OI (1<<3)
-#define SSI_INT_UI (1<<2)
-#define SSI_INT_DI (1<<1)
-
-/* SSI_INTEN */
-#define SSI_INTEN_OIE (1<<3)
-#define SSI_INTEN_UIE (1<<2)
-#define SSI_INTEN_DIE (1<<1)
-
-#define SSI_CONFIG_AO (1<<24)
-#define SSI_CONFIG_DO (1<<23)
-#define SSI_CONFIG_ALEN (7<<20)
-#define SSI_CONFIG_DLEN (15<<16)
-#define SSI_CONFIG_DD (1<<11)
-#define SSI_CONFIG_AD (1<<10)
-#define SSI_CONFIG_BM (3<<8)
-#define SSI_CONFIG_CE (1<<7)
-#define SSI_CONFIG_DP (1<<6)
-#define SSI_CONFIG_DL (1<<5)
-#define SSI_CONFIG_EP (1<<4)
-#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
-#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
-#define SSI_CONFIG_BM_HI (0<<8)
-#define SSI_CONFIG_BM_LO (1<<8)
-#define SSI_CONFIG_BM_CY (2<<8)
-
-#define SSI_ADATA_D (1<<24)
-#define SSI_ADATA_ADDR (0xFF<<16)
-#define SSI_ADATA_DATA (0x0FFF)
-#define SSI_ADATA_ADDR_N(N) (N<<16)
-
-#define SSI_ENABLE_CD (1<<1)
-#define SSI_ENABLE_E (1<<0)
-
-
-/* IrDA Controller */
-#define IRDA_BASE 0xB0300000
-#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
-#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
-#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
-#define IR_RING_SIZE (IRDA_BASE+0x0C)
-#define IR_RING_PROMPT (IRDA_BASE+0x10)
-#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
-#define IR_INT_CLEAR (IRDA_BASE+0x18)
-#define IR_CONFIG_1 (IRDA_BASE+0x20)
-#define IR_RX_INVERT_LED (1<<0)
-#define IR_TX_INVERT_LED (1<<1)
-#define IR_ST (1<<2)
-#define IR_SF (1<<3)
-#define IR_SIR (1<<4)
-#define IR_MIR (1<<5)
-#define IR_FIR (1<<6)
-#define IR_16CRC (1<<7)
-#define IR_TD (1<<8)
-#define IR_RX_ALL (1<<9)
-#define IR_DMA_ENABLE (1<<10)
-#define IR_RX_ENABLE (1<<11)
-#define IR_TX_ENABLE (1<<12)
-#define IR_LOOPBACK (1<<14)
-#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
- IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS (IRDA_BASE+0x24)
-#define IR_ENABLE (IRDA_BASE+0x28)
-#define IR_RX_STATUS (1<<9)
-#define IR_TX_STATUS (1<<10)
-#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
-#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
-#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
-#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
-#define IR_CONFIG_2 (IRDA_BASE+0x3C)
-#define IR_MODE_INV (1<<0)
-#define IR_ONE_PIN (1<<1)
-#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
-
-/* GPIO */
-#define SYS_PINFUNC 0xB190002C
-#define SYS_PF_USB (1<<15) /* 2nd USB device/host */
-#define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
-#define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
-#define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
-#define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
-#define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
-#define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
-#define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
-#define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
-#define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
-#define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
-#define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
-#define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
-#define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
-#define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
-#define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
-#define SYS_TRIOUTRD 0xB1900100
-#define SYS_TRIOUTCLR 0xB1900100
-#define SYS_OUTPUTRD 0xB1900108
-#define SYS_OUTPUTSET 0xB1900108
-#define SYS_OUTPUTCLR 0xB190010C
-#define SYS_PINSTATERD 0xB1900110
-#define SYS_PININPUTEN 0xB1900110
-
-/* GPIO2, Au1500 only */
-#define GPIO2_BASE 0xB1700000
-#define GPIO2_DIR (GPIO2_BASE + 0)
-#define GPIO2_DATA_EN (GPIO2_BASE + 8)
-#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
-#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
-
-/* Power Management */
-#define SYS_SCRATCH0 0xB1900018
-#define SYS_SCRATCH1 0xB190001C
-#define SYS_WAKEMSK 0xB1900034
-#define SYS_ENDIAN 0xB1900038
-#define SYS_POWERCTRL 0xB190003C
-#define SYS_WAKESRC 0xB190005C
-#define SYS_SLPPWR 0xB1900078
-#define SYS_SLEEP 0xB190007C
-
-/* Clock Controller */
-#define SYS_FREQCTRL0 0xB1900020
-#define SYS_FC_FRDIV2_BIT 22
-#define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
-#define SYS_FC_FE2 (1<<21)
-#define SYS_FC_FS2 (1<<20)
-#define SYS_FC_FRDIV1_BIT 12
-#define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
-#define SYS_FC_FE1 (1<<11)
-#define SYS_FC_FS1 (1<<10)
-#define SYS_FC_FRDIV0_BIT 2
-#define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
-#define SYS_FC_FE0 (1<<1)
-#define SYS_FC_FS0 (1<<0)
-#define SYS_FREQCTRL1 0xB1900024
-#define SYS_FC_FRDIV5_BIT 22
-#define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
-#define SYS_FC_FE5 (1<<21)
-#define SYS_FC_FS5 (1<<20)
-#define SYS_FC_FRDIV4_BIT 12
-#define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
-#define SYS_FC_FE4 (1<<11)
-#define SYS_FC_FS4 (1<<10)
-#define SYS_FC_FRDIV3_BIT 2
-#define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
-#define SYS_FC_FE3 (1<<1)
-#define SYS_FC_FS3 (1<<0)
-#define SYS_CLKSRC 0xB1900028
-#define SYS_CS_ME1_BIT 27
-#define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
-#define SYS_CS_DE1 (1<<26)
-#define SYS_CS_CE1 (1<<25)
-#define SYS_CS_ME0_BIT 22
-#define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
-#define SYS_CS_DE0 (1<<21)
-#define SYS_CS_CE0 (1<<20)
-#define SYS_CS_MI2_BIT 17
-#define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
-#define SYS_CS_DI2 (1<<16)
-#define SYS_CS_CI2 (1<<15)
-#define SYS_CS_MUH_BIT 12
-#define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
-#define SYS_CS_DUH (1<<11)
-#define SYS_CS_CUH (1<<10)
-#define SYS_CS_MUD_BIT 7
-#define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
-#define SYS_CS_DUD (1<<6)
-#define SYS_CS_CUD (1<<5)
-#define SYS_CS_MIR_BIT 2
-#define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
-#define SYS_CS_DIR (1<<1)
-#define SYS_CS_CIR (1<<0)
-
-#define SYS_CS_MUX_AUX 0x1
-#define SYS_CS_MUX_FQ0 0x2
-#define SYS_CS_MUX_FQ1 0x3
-#define SYS_CS_MUX_FQ2 0x4
-#define SYS_CS_MUX_FQ3 0x5
-#define SYS_CS_MUX_FQ4 0x6
-#define SYS_CS_MUX_FQ5 0x7
-#define SYS_CPUPLL 0xB1900060
-#define SYS_AUXPLL 0xB1900064
-
-/* AC97 Controller */
-#define AC97C_CONFIG 0xB0000000
-#define AC97C_RECV_SLOTS_BIT 13
-#define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-#define AC97C_XMIT_SLOTS_BIT 3
-#define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-#define AC97C_SG (1<<2)
-#define AC97C_SYNC (1<<1)
-#define AC97C_RESET (1<<0)
-#define AC97C_STATUS 0xB0000004
-#define AC97C_XU (1<<11)
-#define AC97C_XO (1<<10)
-#define AC97C_RU (1<<9)
-#define AC97C_RO (1<<8)
-#define AC97C_READY (1<<7)
-#define AC97C_CP (1<<6)
-#define AC97C_TR (1<<5)
-#define AC97C_TE (1<<4)
-#define AC97C_TF (1<<3)
-#define AC97C_RR (1<<2)
-#define AC97C_RE (1<<1)
-#define AC97C_RF (1<<0)
-#define AC97C_DATA 0xB0000008
-#define AC97C_CMD 0xB000000C
-#define AC97C_WD_BIT 16
-#define AC97C_READ (1<<7)
-#define AC97C_INDEX_MASK 0x7f
-#define AC97C_CNTRL 0xB0000010
-#define AC97C_RS (1<<1)
-#define AC97C_CE (1<<0)
-
-#define DB1000_BCSR_ADDR 0xAE000000
-#define DB1550_BCSR_ADDR 0xAF000000
-
-#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
-
-#ifdef CONFIG_SOC_AU1500
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
-#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
-#define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
-#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
-
-/* All of our structures, like pci resource, have 32 bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
- * addresses. For PCI IO, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
- */
-#define Au1500_EXT_CFG 0x600000000
-#define Au1500_EXT_CFG_TYPE1 0x680000000
-#define Au1500_PCI_IO_START 0x500000000
-#define Au1500_PCI_IO_END 0x5000FFFFF
-#define Au1500_PCI_MEM_START 0x440000000
-#define Au1500_PCI_MEM_END 0x443FFFFFF
-
-#define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
-#define PCI_IO_END (Au1500_PCI_IO_END)
-#define PCI_MEM_START (Au1500_PCI_MEM_START)
-#define PCI_MEM_END (Au1500_PCI_MEM_END)
-#define PCI_FIRST_DEVFN (0<<3)
-#define PCI_LAST_DEVFN (19<<3)
-
-#endif
-
-#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
-/* no PCI bus controller */
-#define PCI_IO_START 0
-#define PCI_IO_END 0
-#define PCI_MEM_START 0
-#define PCI_MEM_END 0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN 0
-#endif
-#define AU1X_SOCK0_IO 0xF00000000
-#define AU1X_SOCK0_PHYS_ATTR 0xF40000000
-#define AU1X_SOCK0_PHYS_MEM 0xF80000000
-
-/* pcmcia socket 1 needs external glue logic so the memory map
- * differs from board to board.
- */
-
-/* Only for db board, not older pb */
-#define AU1X_SOCK1_IO 0xF04000000
-#define AU1X_SOCK1_PHYS_ATTR 0xF44000000
-#define AU1X_SOCK1_PHYS_MEM 0xF84000000
-
-#endif
deleted file mode 100644
@@ -1,27 +0,0 @@
-if TARGET_PB1X00
-
-config SYS_BOARD
- default "pb1x00"
-
-config SYS_SOC
- default "au1x00"
-
-config SYS_CONFIG_NAME
- default "pb1x00"
-
-config SYS_TEXT_BASE
- default 0x83800000
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
deleted file mode 100644
@@ -1,6 +0,0 @@
-PB1X00 BOARD
-#M: -
-S: Maintained
-F: board/pb1x00/
-F: include/configs/pb1x00.h
-F: configs/pb1000_defconfig
deleted file mode 100644
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = pb1x00.o flash.o
-obj-y += lowlevel_init.o
deleted file mode 100644
@@ -1,63 +0,0 @@
-By Thomas.Lange@corelatus.se 2004-Oct-05
-----------------------------------------
-DbAu1xx0 are development boards from AMD containing
-an Alchemy AU1xx0 series cpu with mips32 core.
-Existing cpu:s are Au1000, Au1100, Au1500 and Au1550
-
-Limitations & comments
-----------------------
-Support was originally big endian only.
-I have not tested, but several u-boot users report working
-configurations in little endian mode.
-
-I named the board dbau1x00, to allow
-support for all three development boards
-( dbau1000, dbau1100 and dbau1500 ).
-Now there is a new board called dbau1550 also, which
-should be supported RSN.
-
-I only have a dbau1000, so my testing is limited
-to this board.
-
-The board has two different flash banks, that can
-be selected via dip switch. This makes it possible
-to test new bootloaders without thrashing the YAMON
-boot loader delivered with board.
-
-NOTE! When you switch between the two boot flashes, the
-base addresses will be swapped.
-Have this in mind when you compile u-boot. CONFIG_SYS_TEXT_BASE has
-to match the address where u-boot is located when you
-actually launch.
-
-Ethernet only supported for mac0.
-
-PCMCIA only supported for slot 0, only 3.3V.
-
-PCMCIA IDE tested with Sandisk Compact Flash and
-IBM microdrive.
-
-###################################
-######## NOTE!!!!!! #########
-###################################
-If you partition a disk on another system (e.g. laptop),
-all bytes will be swapped on 16bit level when using
-PCMCIA and running cpu in big endian mode!!!!
-
-This is probably due to an error in Au1000 chip.
-
-Solution:
-
-a) Boot via network and partition disk directly from
-dbau1x00. The endian will then be correct.
-
-b) Partition disk on "laptop" and fill it with all files
-you need. Then write a simple program that endian swaps
-whole disk,
-
-Example:
-Original "laptop" byte order:
-B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
-
-Dbau1000 byte order will then be:
-B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
deleted file mode 100644
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- printf ("Skipping flash_init\n");
- return (0);
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- printf ("write_buff not implemented\n");
- return (-1);
-}
deleted file mode 100644
@@ -1,391 +0,0 @@
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <mach/au1x00.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
-#define AU1500_SYS_ADDR 0xB1900000
-#define sys_endian 0x0038
-#define CP0_Config0 $16
-#define MEM_1MS ((396000000/1000000) * 1000)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 1) Establish CPU endian mode.
- * NOTE: A fair amount of code is necessary on the Pb1000 to
- * obtain the value of Switch S8.1 which is used to determine
- * endian at run-time.
- */
-
- /* RCE1 */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* Set DSTRB bits so switch will read correctly */
- li t1, 0xBE00000C
- lw t2, 0(t1)
- or t2, t2, 0x00000300
- sw t2, 0(t1)
-
- /* Check switch setting */
- li t1, 0xBE000014
- lw t2, 0(t1)
- and t2, t2, 0x00000100
- bne t2, zero, big_endian
- nop
-
-little_endian:
-
- /* Change Au1 core to little endian */
- li t0, AU1500_SYS_ADDR
- li t1, 1
- sw t1, sys_endian(t0)
- mfc0 t2, CP0_CONFIG
- mtc0 t2, CP0_CONFIG
- nop
- nop
-
- /* Big Endian is default so nothing to do but fall through */
-
-big_endian:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
-
- /* RCE0 8MB AMD29D323 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00001403
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0xFFFFFFDD
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11F83FE0
- sw t1, 0(t0)
-
- /* RCE1 CPLD Board Logic */
- li t0, MEM_STCFG1
- li t1, 0x00000083
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x33030A10
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x11803E40
- sw t1, 0(t0)
-
- /* RCE2 CPLD Board Logic */
- li t0, MEM_STCFG2
- li t1, 0x00000004
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x08061908
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x12A03FC0
- sw t1, 0(t0)
-
- /* RCE3 PCMCIA 250ns */
- li t0, MEM_STCFG3
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10000000
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /*
- * Skip memory setup if we are running from memory
- */
- li t0, 0x90000000
- sub t0, ra, t0
- bltz t0, skip_memsetup
- nop
-
- /*
- * SDCS0 - Not used, for SMROM
- * SDCS1 - 32MB Micron 48LCBM16A2
- * SDCS2 - 32MB Micron 48LCBM16A2
- */
- li t0, MEM_SDMODE0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00552229
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR1
- li t1, 0x001003F8
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x001023F8
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x74000c30 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x76000c30 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD1
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD2
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-skip_memsetup:
-
- li t0, SYS_PINFUNC
- li t1, 0/*0x00008080*/
- sw t1, 0(t0)
-
- /*
- li t0, SYS_TRIOUTCLR
- li t1, 0x00001FFF
- sw t1, 0(t0)
-
- li t0, SYS_OUTPUTCLR
- li t1, 0x00008000
- sw t1, 0(t0)
- */
- sync
-
- jr ra
- nop
deleted file mode 100644
@@ -1,108 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2003
- * Thomas.Lange@corelatus.se
- */
-
-#include <common.h>
-#include <command.h>
-#include <mach/au1x00.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- gd->ram_size = 64 * 1024 * 1024;
-
- return 0;
-}
-
-#define BCSR_PCMCIA_PC0DRVEN 0x0010
-#define BCSR_PCMCIA_PC0RST 0x0080
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-int checkboard (void)
-{
-#if defined(CONFIG_IDE_PCMCIA) && 0
- u16 status;
-#endif
- /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- u32 proc_id;
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: Pb1000\n");
- printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 1:
- puts ("Board: Pb1500\n");
- printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- case 2:
- puts ("Board: Pb1100\n");
- printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#if defined(CONFIG_IDE_PCMCIA) && 0
- /* Enable 3.3 V on slot 0 ( VCC )
- No 5V */
- status = 4;
- *pcmcia_bcsr = status;
-
- status |= BCSR_PCMCIA_PC0DRVEN;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(300*1000);
-
- status |= BCSR_PCMCIA_PC0RST;
- *pcmcia_bcsr = status;
- au_sync();
-
- udelay(100*1000);
-
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
-
-#if 0
- /* We dont need theese unless we run whole pcmcia package */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-#endif /* 0 */
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-#endif /* CONFIG_IDE_PCMCIA */
-
- return 0;
-}
deleted file mode 100644
@@ -1,20 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_TARGET_PB1X00=y
-CONFIG_SYS_EXTRA_OPTIONS="PB1000"
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="Pb1x00 # "
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_RUN is not set
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_MTD_NOR_FLASH=y
deleted file mode 100644
@@ -1,138 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * This file contains the configuration parameters for the dbau1x00 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-
-#ifdef CONFIG_PB1000
-#define CONFIG_SOC_AU1000 1
-#else
-#ifdef CONFIG_PB1100
-#define CONFIG_SOC_AU1100 1
-#else
-#ifdef CONFIG_PB1500
-#define CONFIG_SOC_AU1500 1
-#else
-#error "No valid board set"
-#endif
-#endif
-#endif
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "bootfile=/vmlinux.img\0" \
- "load=tftp 80500000 ${u-boot}\0" \
- ""
-/* Boot from NFS root */
-#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ 396000000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#undef CONFIG_SYS_MEMTEST_START
-#define CONFIG_SYS_MEMTEST_START 0x80200000
-#define CONFIG_SYS_MEMTEST_END 0x83800000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
-#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x4000000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0030000
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS 2
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-/*---USB -------------------------------------------*/
-#if 0
-#define CONFIG_USB_OHCI
-#endif
-
-/*---ATA PCMCIA ------------------------------------*/
-#if 0
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 8
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
-
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-#endif /* __CONFIG_H */
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an apparent clone of the dbau1x00 platform. As pb1x00 had no listed maintainer I am assuming that it is also orphaned. Remove this platform and then remove the unused SoC support. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> --- arch/mips/Kconfig | 10 - arch/mips/Makefile | 1 - arch/mips/include/asm/addrspace.h | 6 +- arch/mips/mach-au1x00/Makefile | 6 - arch/mips/mach-au1x00/au1x00_eth.c | 307 ----- arch/mips/mach-au1x00/au1x00_ide.c | 14 - arch/mips/mach-au1x00/au1x00_serial.c | 130 --- arch/mips/mach-au1x00/au1x00_usb_ohci.c | 1609 --------------------------- arch/mips/mach-au1x00/au1x00_usb_ohci.h | 416 ------- arch/mips/mach-au1x00/include/mach/au1x00.h | 1040 ----------------- board/pb1x00/Kconfig | 27 - board/pb1x00/MAINTAINERS | 6 - board/pb1x00/Makefile | 7 - board/pb1x00/README | 63 -- board/pb1x00/flash.c | 26 - board/pb1x00/lowlevel_init.S | 391 ------- board/pb1x00/pb1x00.c | 108 -- configs/pb1000_defconfig | 20 - include/configs/pb1x00.h | 138 --- 19 files changed, 3 insertions(+), 4322 deletions(-) delete mode 100644 arch/mips/mach-au1x00/Makefile delete mode 100644 arch/mips/mach-au1x00/au1x00_eth.c delete mode 100644 arch/mips/mach-au1x00/au1x00_ide.c delete mode 100644 arch/mips/mach-au1x00/au1x00_serial.c delete mode 100644 arch/mips/mach-au1x00/au1x00_usb_ohci.c delete mode 100644 arch/mips/mach-au1x00/au1x00_usb_ohci.h delete mode 100644 arch/mips/mach-au1x00/include/mach/au1x00.h delete mode 100644 board/pb1x00/Kconfig delete mode 100644 board/pb1x00/MAINTAINERS delete mode 100644 board/pb1x00/Makefile delete mode 100644 board/pb1x00/README delete mode 100644 board/pb1x00/flash.c delete mode 100644 board/pb1x00/lowlevel_init.S delete mode 100644 board/pb1x00/pb1x00.c delete mode 100644 configs/pb1000_defconfig delete mode 100644 include/configs/pb1x00.h