From patchwork Wed May 4 15:53:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Valentin Longchamp X-Patchwork-Id: 94079 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6E3FAB6F57 for ; Thu, 5 May 2011 01:54:50 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B1C872808C; Wed, 4 May 2011 17:54:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BpIBwVIk6Zai; Wed, 4 May 2011 17:54:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 619482809B; Wed, 4 May 2011 17:54:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D439628091 for ; Wed, 4 May 2011 17:54:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JYgvs48aW24p for ; Wed, 4 May 2011 17:53:59 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.ch.keymile.com (mail.ch.keymile.com [193.17.201.103]) by theia.denx.de (Postfix) with SMTP id 06CB928090 for ; Wed, 4 May 2011 17:53:55 +0200 (CEST) Received: from SRVCHBER1212.ch.keymile.net ([172.31.32.9]) by eSafe SMTP Relay 1297237168; Wed, 04 May 2011 17:41:43 +0100 Received: from localhost.localdomain ([172.31.32.134]) by SRVCHBER1212.ch.keymile.net with Microsoft SMTPSVC(6.0.3790.4675); Wed, 4 May 2011 17:53:54 +0200 From: Valentin Longchamp To: u-boot@lists.denx.de Date: Wed, 4 May 2011 17:53:50 +0200 Message-Id: X-Mailer: git-send-email 1.7.0.5 In-Reply-To: In-Reply-To: References: References: X-OriginalArrivalTime: 04 May 2011 15:53:54.0420 (UTC) FILETIME=[78636B40:01CC0A73] X-ESAFE-STATUS: Mail allowed X-ESAFE-DETAILS: Cc: Valentin Longchamp , Detlev@theia.denx.de, holger.brunck@keymile.com Subject: [U-Boot] [PATCH v3 8/8] arm/km: update mgcoge3un board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Holger Brunck We change default settings for egiga on mgcoge3un. The reason we need this is that we have the gig port on mgcoge3un connected using a back-to-back pair of PHYs. There are no magnetics and because of that the port has to be run with a fixd configuration and auto-negotiation must be disabled. In the default mode the egiga driver uses autoneg to determine port speed - which defaults to 1G (we need 100M full duplex). Add wait for the GPIO line connected to mgcoge3ne before starting mgcoge3un. A board specific ethernet present function was added, because on this board ethernet is always present. The BOCO FPGA access was enhanced and changed to use register definitions. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp Acked-by: Heiko Schocher cc: Wolfgang Denk cc: Detlev Zundel cc: Prafulla Wadaskar --- Changes for v2: - split up first large patch series to three independent smaller patch series Changes for v3: - taken Prafulla's comments into account, merged with previous 08/08 patch board/keymile/km_arm/km_arm.c | 80 +++++++++++++++++++++++++++++++++------- include/configs/mgcoge3un.h | 25 +++++++++++++ 2 files changed, 91 insertions(+), 14 deletions(-) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 4049a4e..d86acc9 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -41,6 +41,16 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * BOCO FPGA definitions + */ +#define BOCO 0x10 +#define REG_CTRL_H 0x02 +#define MASK_WRL_UNITRUN 0x01 +#define MASK_RBX_PGY_PRESENT 0x40 +#define REG_IRQ_CIRQ2 0x2d +#define MASK_RBI_DEFECT_16 0x01 + /* Multi-Purpose Pins Functionality configuration */ u32 kwmpp_config[] = { MPP0_NF_IO2, @@ -102,43 +112,64 @@ u32 kwmpp_config[] = { 0 }; +#if defined(CONFIG_MGCOGE3UN) +/* + * Wait for startup OK from mgcoge3ne + */ +int startup_allowed(void) +{ + unsigned char buf; + + /* + * Read CIRQ16 bit (bit 0) + */ + if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0) + printf("%s: Error reading Boco\n", __func__); + else + if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16) + return 1; + return 0; +} + +/* + * mgcoge3un has always ethernet present. Its connected to the 6061 switch + * and provides ICNev and piggy4 connections. + */ +int ethernet_present(void) +{ + return 1; +} +#else int ethernet_present(void) { uchar buf; int ret = 0; - if (i2c_read(0x10, 2, 1, &buf, 1) != 0) { + if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error reading Boco\n", __func__); return -1; } - if ((buf & 0x40) == 0x40) + if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) ret = 1; return ret; } +#endif int initialize_unit_leds(void) { /* - * init the unit LEDs - * per default they all are + * Init the unit LEDs per default they all are * ok apart from bootstat - * LED connected through BOCO - * BOCO lies at the address 0x10 - * LEDs are in the block CTRL_H (addr 0x02) - * BOOTSTAT LED is the first 0x01 */ - #define BOCO 0x10 - #define CTRL_H 0x02 - #define APPLEDMASK 0x01 uchar buf; - if (i2c_read(BOCO, CTRL_H, 1, &buf, 1) != 0) { + if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error reading Boco\n", __func__); return -1; } - buf |= APPLEDMASK; - if (i2c_write(BOCO, CTRL_H, 1, &buf, 1) != 0) { + buf |= MASK_WRL_UNITRUN; + if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { printf("%s: Error writing Boco\n", __func__); return -1; } @@ -167,6 +198,27 @@ int misc_init_r(void) printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); gd->bd->bi_arch_number = mach_type; } +#if defined(CONFIG_MGCOGE3UN) + char *wait_for_ne; + wait_for_ne = getenv("waitforne"); + if (wait_for_ne != NULL) { + if (strcmp(wait_for_ne, "true") == 0) { + int cnt = 0; + puts("NE go: "); + while (startup_allowed() == 0) { + udelay(200000); + cnt++; + if (cnt == 5) + puts("wait\b\b\b\b"); + if (cnt == 10) { + cnt = 0; + puts(" \b\b\b\b"); + } + } + puts("OK\n"); + } + } +#endif initialize_unit_leds(); set_km_env(); diff --git a/include/configs/mgcoge3un.h b/include/configs/mgcoge3un.h index 1c32085..d022c4f 100644 --- a/include/configs/mgcoge3un.h +++ b/include/configs/mgcoge3un.h @@ -50,4 +50,29 @@ /* we use a new RAM type on mgcoge3un board */ #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg +/* + * mgcoge3un has a fixed link to the marvell switch + * with 100MB full duplex and autoneg off, for this + * reason we have to change the default settings + */ +#define PORT_SERIAL_CONTROL_VALUE ( \ + MVGBE_FORCE_LINK_PASS | \ + MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ + MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ + MVGBE_ADV_NO_FLOW_CTRL | \ + MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ + MVGBE_FORCE_BP_MODE_NO_JAM | \ + (1 << 9) /* Reserved bit has to be 1 */ | \ + MVGBE_DO_NOT_FORCE_LINK_FAIL | \ + MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ + MVGBE_DTE_ADV_0 | \ + MVGBE_MIIPHY_MAC_MODE | \ + MVGBE_AUTO_NEG_NO_CHANGE | \ + MVGBE_MAX_RX_PACKET_1552BYTE | \ + MVGBE_CLR_EXT_LOOPBACK | \ + MVGBE_SET_FULL_DUPLEX_MODE | \ + MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ + MVGBE_SET_GMII_SPEED_TO_10_100 |\ + MVGBE_SET_MII_SPEED_TO_100) + #endif /* _CONFIG_MGCOGE3UN_H */