[v4,11/14] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller

Message ID 20180705124011.7661-12-miquel.raynal@bootlin.com
State Changes Requested
Headers show
  • Add System Error Interrupt support to Armada SoCs
Related show

Commit Message

Miquel Raynal July 5, 2018, 12:40 p.m.
Describe the System Error Interrupt (SEI) controller. It aggregates two
types of interrupts, wired and MSIs from respectively the AP and the
CPs, into a single SPI interrupt.

Suggested-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
 .../bindings/interrupt-controller/marvell,sei.txt  | 39 ++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt


diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
new file mode 100644
index 000000000000..9aee3820f1a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt
@@ -0,0 +1,39 @@ 
+Marvell SEI (System Error Interrupt) Controller
+Marvell SEI (System Error Interrupt) controller is an interrupt
+aggregator. It receives interrupts from several sources and aggregates
+them to a single interrupt line (an SPI) on the parent interrupt
+This interrupt controller can handle up to 64 SEIs, a set comes from the
+AP and is wired while a second set comes from the CPs by the mean of
+MSIs. Each 'domain' is represented as a subnode.
+Required properties:
+- compatible: should be "marvell,armada-8k-sei".
+- reg: SEI registers location and length.
+- interrupts: identifies the parent IRQ that will be triggered.
+- marvell,sei-ranges: two ranges, the first one describe wired
+                      interrupts coming from the AP, the second one
+                      non-wired interrupts (MSI) from the CPs.
+- #interrupt-cells: number of cells to define an SEI wired interrupt
+                    coming from the AP, should be 1. The cell is the IRQ
+                    number.
+- interrupt-controller: identifies the node as an interrupt controller
+                        (AP only).
+- msi-controller: identifies the node as an MSI controller (CPs only).
+        sei: interrupt-controller@3f0200 {
+                compatible = "marvell,armada-8k-sei";
+                reg = <0x3f0200 0x40>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+                marvell,sei-ap-ranges = <0 21>;
+                marvell,sei-cp-ranges = <21 43>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                msi-controller;
+        };