From patchwork Wed May 4 00:59:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 93951 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D524B6F59 for ; Wed, 4 May 2011 11:06:18 +1000 (EST) Received: from localhost ([::1]:34072 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQXf-0005zW-EH for incoming@patchwork.ozlabs.org; Tue, 03 May 2011 21:06:15 -0400 Received: from eggs.gnu.org ([140.186.70.92]:53043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQS2-0004ce-G9 for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHQS1-0000l6-Fb for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:26 -0400 Received: from mail-ew0-f45.google.com ([209.85.215.45]:56465) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHQS1-0000ZL-Am for qemu-devel@nongnu.org; Tue, 03 May 2011 21:00:25 -0400 Received: by mail-ew0-f45.google.com with SMTP id 24so221435ewy.4 for ; Tue, 03 May 2011 18:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=5XWOSnY8YfOf7DADSXIE3VtlEFRHyz/bNr8KQDh6zHM=; b=RtdJAoKuQN59OkFIOVmwEMeNfw3myYDV5zZBvTAKb63A9lAKQtlgvKuLgjHa0bQQ6/ 7uXyx4CW+preG6l36jB0e8Qntbdmd6IwZ7YdD3XIuOZWBbfYQckzioBBJZB+MJG97S7S Mi5YVLvJZjE9HCOhagSNJChMaMIb0ykS6dKNw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=oWG1gTjqVBxB0Ud/NlzpOhlBL7ScFFPyZBO3RCBQzR4WoRli4MSOf6ydMT1kXb0Xr9 5i5NPVRmT+nD3Pmn3Q95m+ZrWj50LBKa1KSQNEqZhYa9ghCUHXXK3xmIVk1+IRvrNJ6D 27IfIG2WwEkAmkpzLipiycdFrt9WrPF3BMu/s= Received: by 10.14.15.135 with SMTP id f7mr228430eef.69.1304470824750; Tue, 03 May 2011 18:00:24 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id y18sm435377eeh.22.2011.05.03.18.00.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 03 May 2011 18:00:24 -0700 (PDT) Received: by octofox.metropolis (sSMTP sendmail emulation); Wed, 4 May 2011 05:00:22 +0400 From: Max Filippov To: qemu-devel@nongnu.org Date: Wed, 4 May 2011 04:59:11 +0400 Message-Id: <1304470768-16924-11-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.215.45 Cc: Max Filippov Subject: [Qemu-devel] [RFC 11/28] target-xtensa: implement RST3 group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org - access to Special Registers (wsr, rsr); - access to User Registers (wur, rur); - misc. operations option (value clamp, sign extension, min, max); - conditional moves. Signed-off-by: Max Filippov --- target-xtensa/translate.c | 147 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 147 insertions(+), 0 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index f1f01bc..031873e 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -102,6 +102,32 @@ void xtensa_translate_init(void) } } +static void gen_rsr(TCGv_i32 d, int sr) +{ + if (sregnames[sr]) { + tcg_gen_mov_i32(d, cpu_SR[sr]); + } else { + printf("SR %d not implemented, ", sr); + } +} + +static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) +{ + static void (* const wsr_handler[256])(DisasContext *dc, + uint32_t sr, TCGv_i32 v) = { + }; + + if (sregnames[sr]) { + if (wsr_handler[sr]) { + wsr_handler[sr](dc, sr, s); + } else { + tcg_gen_mov_i32(cpu_SR[sr], s); + } + } else { + printf("SR %d not implemented, ", sr); + } +} + static void gen_exception(int excp) { TCGv_i32 tmp = tcg_const_i32(excp); @@ -172,6 +198,8 @@ static void disas_xtensa_insn(DisasContext *dc) #define BRI8_IMM8 RRI8_IMM8 #define BRI8_IMM8_SE RRI8_IMM8_SE +#define RSR_SR (_b1) + uint8_t _b0 = ldub_code(dc->pc); uint8_t _b1 = ldub_code(dc->pc + 1); uint8_t _b2 = ldub_code(dc->pc + 2); @@ -336,6 +364,125 @@ static void disas_xtensa_insn(DisasContext *dc) break; case 3: /*RST3*/ + switch (_OP2) { + case 0: /*RSR*/ + gen_rsr(cpu_R[RRR_T], RSR_SR); + break; + + case 1: /*WSR*/ + gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); + break; + + case 2: /*SEXTu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 24 - RRR_T); + tcg_gen_sari_i32(cpu_R[RRR_R], tmp, 24 - RRR_T); + tcg_temp_free(tmp); + } + break; + + case 3: /*CLAMPSu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i32 tmp2 = tcg_temp_new_i32(); + int label = gen_new_label(); + + tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T); + tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]); + tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7)); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp2, 0, label); + + tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31); + tcg_gen_xori_i32(cpu_R[RRR_R], tmp1, + 0xffffffff >> (25 - RRR_T)); + + gen_set_label(label); + + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); + } + break; + + case 4: /*MINu*/ + case 5: /*MAXu*/ + case 6: /*MINUu*/ + case 7: /*MAXUu*/ + HAS_OPTION(XTENSA_OPTION_MISC_OP); + { + static const TCGCond cond[] = { + TCG_COND_LE, + TCG_COND_GE, + TCG_COND_LEU, + TCG_COND_GEU + }; + int label = gen_new_label(); + + if (RRR_R != RRR_T) { + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + tcg_gen_brcond_i32(cond[_OP2 - 4], + cpu_R[RRR_S], cpu_R[RRR_T], label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]); + } else { + tcg_gen_brcond_i32(cond[_OP2 - 4], + cpu_R[RRR_T], cpu_R[RRR_S], label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + } + gen_set_label(label); + } + break; + + case 8: /*MOVEQZ*/ + case 9: /*MOVNEZ*/ + case 10: /*MOVLTZ*/ + case 11: /*MOVGEZ*/ + { + static const TCGCond cond[] = { + TCG_COND_NE, + TCG_COND_EQ, + TCG_COND_GE, + TCG_COND_LT + }; + int label = gen_new_label(); + tcg_gen_brcondi_i32(cond[_OP2 - 8], cpu_R[RRR_T], 0, label); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_S]); + gen_set_label(label); + } + break; + + case 12: /*MOVFp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 13: /*MOVTp*/ + HAS_OPTION(XTENSA_OPTION_BOOLEAN); + break; + + case 14: /*RUR*/ + { + int st = (RRR_S << 4) + RRR_T; + if (uregnames[st]) { + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); + } else { + printf("rur %d not implemented, ", st); + } + } + break; + + case 15: /*WUR*/ + { + if (uregnames[RSR_SR]) { + tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); + } else { + printf("wur %d not implemented, ", RSR_SR); + } + } + break; + + } break; case 4: /*EXTUI*/