diff mbox series

[v4,15/18] fadump: Send OPAL relocated base address to SBE

Message ID 20180703061727.8789-16-hegdevasant@linux.vnet.ibm.com
State Superseded
Headers show
Series MPIPL support | expand

Commit Message

Vasant Hegde July 3, 2018, 6:17 a.m. UTC
OPAL relocates itself during boot. During memory preserving IPL hostboot needs
to access relocated OPAL to get MDST, MDDT tables. Hence send relocated base
address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send
stashed data to hostboot... so that hostboot can access these data.

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
 core/opal-mpipl.c |  4 ++++
 hw/sbe-p9.c       | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 include/sbe-p9.h  |  6 ++++++
 3 files changed, 57 insertions(+)

Comments

Stewart Smith Aug. 7, 2018, 8:02 a.m. UTC | #1
Vasant Hegde <hegdevasant@linux.vnet.ibm.com> writes:
> OPAL relocates itself during boot. During memory preserving IPL hostboot needs
> to access relocated OPAL to get MDST, MDDT tables. Hence send relocated base
> address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send
> stashed data to hostboot... so that hostboot can access these data.
>
> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
> ---
>  core/opal-mpipl.c |  4 ++++
>  hw/sbe-p9.c       | 47 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/sbe-p9.h  |  6 ++++++
>  3 files changed, 57 insertions(+)
>
> diff --git a/core/opal-mpipl.c b/core/opal-mpipl.c
> index 455ecbd2a..6f6016a46 100644
> --- a/core/opal-mpipl.c
> +++ b/core/opal-mpipl.c
> @@ -23,6 +23,7 @@
>  #include <opal.h>
>  #include <opal-dump.h>
>  #include <opal-internal.h>
> +#include <sbe-p9.h>
>  #include <skiboot.h>
>
>  #include <ccan/endian/endian.h>
> @@ -348,6 +349,9 @@ void opal_fadump_init(void)
>
>  	adjust_opal_dump_size(dump_node);
>
> +	/* Send OPAL relocated base address to SBE */
> +	p9_sbe_send_relocated_base(SKIBOOT_BASE);
> +
>  	/* OPAL interface */
>  	opal_register(OPAL_FADUMP_MANAGE, opal_fadump_manage, 3);
>  }
> diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c
> index d52ada15a..b05a4ec0f 100644
> --- a/hw/sbe-p9.c
> +++ b/hw/sbe-p9.c
> @@ -861,6 +861,53 @@ bool p9_sbe_timer_ok(void)
>  	return sbe_has_timer;
>  }
>
> +static void p9_sbe_stash_chipop_resp(struct p9_sbe_msg *msg)
> +{
> +	int rc = p9_sbe_get_primary_rc(msg->resp);
> +	struct p9_sbe *sbe = (void *)msg->user_data;
> +
> +	if (rc == SBE_STATUS_PRI_SUCCESS) {
> +		prlog(PR_DEBUG, "Sent stash MPIPL config [chip id =0x%x]\n",
> +		      sbe->chip_id);
> +	} else {
> +		prlog(PR_DEBUG, "Failed to send stash MPIPL config "
> +		      "[chip id = 0x%x, rc = %d]\n", sbe->chip_id, rc);

Should this be PR_ERR in the case where hostboot told us mpipl is supported?
Vasant Hegde Aug. 16, 2018, 4:54 a.m. UTC | #2
On 08/07/2018 01:32 PM, Stewart Smith wrote:
> Vasant Hegde <hegdevasant@linux.vnet.ibm.com> writes:
>> OPAL relocates itself during boot. During memory preserving IPL hostboot needs
>> to access relocated OPAL to get MDST, MDDT tables. Hence send relocated base
>> address to SBE via 'stash MPIPL config' chip-op. During next IPL SBE will send
>> stashed data to hostboot... so that hostboot can access these data.
>>
>> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
>> ---

.../...

>> +static void p9_sbe_stash_chipop_resp(struct p9_sbe_msg *msg)
>> +{
>> +	int rc = p9_sbe_get_primary_rc(msg->resp);
>> +	struct p9_sbe *sbe = (void *)msg->user_data;
>> +
>> +	if (rc == SBE_STATUS_PRI_SUCCESS) {
>> +		prlog(PR_DEBUG, "Sent stash MPIPL config [chip id =0x%x]\n",
>> +		      sbe->chip_id);
>> +	} else {
>> +		prlog(PR_DEBUG, "Failed to send stash MPIPL config "
>> +		      "[chip id = 0x%x, rc = %d]\n", sbe->chip_id, rc);
> 
> Should this be PR_ERR in the case where hostboot told us mpipl is supported?
> 

Agree. Will fix in v5.

-Vasant
diff mbox series

Patch

diff --git a/core/opal-mpipl.c b/core/opal-mpipl.c
index 455ecbd2a..6f6016a46 100644
--- a/core/opal-mpipl.c
+++ b/core/opal-mpipl.c
@@ -23,6 +23,7 @@ 
 #include <opal.h>
 #include <opal-dump.h>
 #include <opal-internal.h>
+#include <sbe-p9.h>
 #include <skiboot.h>
 
 #include <ccan/endian/endian.h>
@@ -348,6 +349,9 @@  void opal_fadump_init(void)
 
 	adjust_opal_dump_size(dump_node);
 
+	/* Send OPAL relocated base address to SBE */
+	p9_sbe_send_relocated_base(SKIBOOT_BASE);
+
 	/* OPAL interface */
 	opal_register(OPAL_FADUMP_MANAGE, opal_fadump_manage, 3);
 }
diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c
index d52ada15a..b05a4ec0f 100644
--- a/hw/sbe-p9.c
+++ b/hw/sbe-p9.c
@@ -861,6 +861,53 @@  bool p9_sbe_timer_ok(void)
 	return sbe_has_timer;
 }
 
+static void p9_sbe_stash_chipop_resp(struct p9_sbe_msg *msg)
+{
+	int rc = p9_sbe_get_primary_rc(msg->resp);
+	struct p9_sbe *sbe = (void *)msg->user_data;
+
+	if (rc == SBE_STATUS_PRI_SUCCESS) {
+		prlog(PR_DEBUG, "Sent stash MPIPL config [chip id =0x%x]\n",
+		      sbe->chip_id);
+	} else {
+		prlog(PR_DEBUG, "Failed to send stash MPIPL config "
+		      "[chip id = 0x%x, rc = %d]\n", sbe->chip_id, rc);
+	}
+
+	p9_sbe_freemsg(msg);
+}
+
+static void __p9_sbe_send_relocated_base(struct p9_sbe *sbe, u64 reloc_base)
+{
+	u8 key = SBE_STASH_KEY_SKIBOOT_BASE;
+	u16 cmd = SBE_CMD_STASH_MPIPL_CONFIG;
+	u16 flag = SBE_CMD_CTRL_RESP_REQ;
+	struct p9_sbe_msg *msg;
+
+	msg = p9_sbe_mkmsg(cmd, flag, key, reloc_base, 0);
+	if (!msg) {
+		prlog(PR_DEBUG, "Message allocation failed\n");
+		return;
+	}
+	msg->user_data = (void *)sbe;
+	if (p9_sbe_queue_msg(sbe->chip_id, msg, p9_sbe_stash_chipop_resp)) {
+		prlog(PR_ERR, "Failed to queue stash MPIPL config message\n");
+	}
+}
+
+/* Send relocated skiboot base address to all SBE */
+void p9_sbe_send_relocated_base(uint64_t reloc_base)
+{
+	struct proc_chip *chip;
+
+	for_each_chip(chip) {
+		if (chip->sbe == NULL)
+			continue;
+
+		__p9_sbe_send_relocated_base(chip->sbe, reloc_base);
+	}
+}
+
 void p9_sbe_init(void)
 {
 	struct dt_node *xn;
diff --git a/include/sbe-p9.h b/include/sbe-p9.h
index 4b839d8ba..5f36cb39e 100644
--- a/include/sbe-p9.h
+++ b/include/sbe-p9.h
@@ -159,6 +159,9 @@ 
 #define CONTROL_TIMER_START		0x0001
 #define CONTROL_TIMER_STOP		0x0002
 
+/* Stash MPIPL config */
+#define SBE_STASH_KEY_SKIBOOT_BASE	0x03
+
 /* SBE message state */
 enum p9_sbe_msg_state {
 	sbe_msg_unused = 0,	/* Free */
@@ -237,4 +240,7 @@  extern bool p9_sbe_timer_ok(void);
 /* Update SBE timer expiry */
 extern void p9_sbe_update_timer_expiry(uint64_t new_target);
 
+/* Send skiboot relocated base address to SBE */
+extern void p9_sbe_send_relocated_base(uint64_t reloc_base);
+
 #endif	/* __SBE_P9_H */