===================================================================
@@ -18,6 +18,9 @@
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
+HeaderInclude
+config/mips/mips-opts.h
+
EB
Driver
@@ -25,9 +28,28 @@ EL
Driver
mabi=
-Target RejectNegative Joined
+Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
-mabi=ABI Generate code that conforms to the given ABI
+Enum
+Name(mips_abi) Type(int)
+Known MIPS ABIs (for use with the -mabi= option):
+
+EnumValue
+Enum(mips_abi) String(32) Value(ABI_32)
+
+EnumValue
+Enum(mips_abi) String(o64) Value(ABI_O64)
+
+EnumValue
+Enum(mips_abi) String(n32) Value(ABI_N32)
+
+EnumValue
+Enum(mips_abi) String(64) Value(ABI_64)
+
+EnumValue
+Enum(mips_abi) String(eabi) Value(ABI_EABI)
+
mabicalls
Target Report Mask(ABICALLS)
Generate code that can be used in SVR4-style dynamic objects
@@ -57,9 +79,22 @@ Target Report Mask(CHECK_ZERO_DIV)
Trap on integer divide by zero
mcode-readable=
-Target RejectNegative Joined
+Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
-mcode-readable=SETTING Specify when instructions are allowed to access code
+Enum
+Name(mips_code_readable_setting) Type(enum mips_code_readable_setting)
+Valid arguments to -mcode-readable=:
+
+EnumValue
+Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES)
+
+EnumValue
+Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL)
+
+EnumValue
+Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
+
mdivide-breaks
Target Report RejectNegative Mask(DIVIDE_BREAKS)
Use branch-and-break sequences to check for integer divide by zero
@@ -255,9 +290,22 @@ Target Report Mask(PAIRED_SINGLE_FLOAT)
Use paired-single floating-point instructions
mr10k-cache-barrier=
-Target Joined RejectNegative
+Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
-mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted
+Enum
+Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting)
+Valid arguments to -mr10k-cache-barrier=:
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE)
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE)
+
+EnumValue
+Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
+
mrelax-pic-calls
Target Report Mask(RELAX_PIC_CALLS)
Try to allow the linker to turn PIC calls into direct calls
===================================================================
@@ -0,0 +1,39 @@
+/* Definitions for option handling for MIPS.
+ Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
+ Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef MIPS_OPTS_H
+#define MIPS_OPTS_H
+
+/* Enumerates the setting of the -mcode-readable option. */
+enum mips_code_readable_setting {
+ CODE_READABLE_NO,
+ CODE_READABLE_PCREL,
+ CODE_READABLE_YES
+};
+
+/* Enumerates the setting of the -mr10k-cache-barrier option. */
+enum mips_r10k_cache_barrier_setting {
+ R10K_CACHE_BARRIER_NONE,
+ R10K_CACHE_BARRIER_STORE,
+ R10K_CACHE_BARRIER_LOAD_STORE
+};
+
+#endif
===================================================================
@@ -182,13 +182,6 @@ enum mips_address_type {
ADDRESS_SYMBOLIC
};
-/* Enumerates the setting of the -mr10k-cache-barrier option. */
-enum mips_r10k_cache_barrier_setting {
- R10K_CACHE_BARRIER_NONE,
- R10K_CACHE_BARRIER_STORE,
- R10K_CACHE_BARRIER_LOAD_STORE
-};
-
/* Macros to create an enumeration identifier for a function prototype. */
#define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
#define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
@@ -531,9 +524,6 @@ int mips_isa;
/* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
static const struct mips_cpu_info *mips_isa_option_info;
-/* Which ABI to use. */
-int mips_abi = MIPS_ABI_DEFAULT;
-
/* Which cost information to use. */
static const struct mips_rtx_cost_data *mips_cost;
@@ -551,12 +541,6 @@ static int mips_base_align_loops; /* ali
static int mips_base_align_jumps; /* align_jumps */
static int mips_base_align_functions; /* align_functions */
-/* The -mcode-readable setting. */
-enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
-
-/* The -mr10k-cache-barrier setting. */
-static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
-
/* Index [M][R] is true if register R is allowed to hold a value of mode M. */
bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
@@ -15464,21 +15448,6 @@ mips_handle_option (struct gcc_options *
switch (code)
{
- case OPT_mabi_:
- if (strcmp (arg, "32") == 0)
- mips_abi = ABI_32;
- else if (strcmp (arg, "o64") == 0)
- mips_abi = ABI_O64;
- else if (strcmp (arg, "n32") == 0)
- mips_abi = ABI_N32;
- else if (strcmp (arg, "64") == 0)
- mips_abi = ABI_64;
- else if (strcmp (arg, "eabi") == 0)
- mips_abi = ABI_EABI;
- else
- return false;
- return true;
-
case OPT_march_:
case OPT_mtune_:
return mips_parse_cpu (arg) != 0;
@@ -15488,29 +15457,7 @@ mips_handle_option (struct gcc_options *
return mips_isa_option_info != 0;
case OPT_mno_flush_func:
- mips_cache_flush_func = NULL;
- return true;
-
- case OPT_mcode_readable_:
- if (strcmp (arg, "yes") == 0)
- mips_code_readable = CODE_READABLE_YES;
- else if (strcmp (arg, "pcrel") == 0)
- mips_code_readable = CODE_READABLE_PCREL;
- else if (strcmp (arg, "no") == 0)
- mips_code_readable = CODE_READABLE_NO;
- else
- return false;
- return true;
-
- case OPT_mr10k_cache_barrier_:
- if (strcmp (arg, "load-store") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
- else if (strcmp (arg, "store") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
- else if (strcmp (arg, "none") == 0)
- mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
- else
- return false;
+ opts->x_mips_cache_flush_func = NULL;
return true;
default:
===================================================================
@@ -72,12 +72,7 @@ struct mips_cpu_info {
unsigned int tune_flags;
};
-/* Enumerates the setting of the -mcode-readable option. */
-enum mips_code_readable_setting {
- CODE_READABLE_NO,
- CODE_READABLE_PCREL,
- CODE_READABLE_YES
-};
+#include "config/mips/mips-opts.h"
/* Macros to silence warnings about numbers being signed in traditional
C and unsigned in ISO C when compiled on 32-bit hosts. */
@@ -2896,11 +2891,9 @@ extern bool mips_split_hi_p[];
extern enum processor mips_arch; /* which cpu to codegen for */
extern enum processor mips_tune; /* which cpu to schedule for */
extern int mips_isa; /* architectural level */
-extern int mips_abi; /* which ABI to use */
extern const struct mips_cpu_info *mips_arch_info;
extern const struct mips_cpu_info *mips_tune_info;
extern bool mips_base_mips16;
-extern enum mips_code_readable_setting mips_code_readable;
extern GTY(()) struct target_globals *mips16_globals;
#endif