| Submitter | Shinya Kuribayashi |
|---|---|
| Date | May 3, 2011, 12:31 p.m. |
| Message ID | <4DBFF5A9.70605@pobox.com> |
| Download | mbox | patch |
| Permalink | /patch/93781/ |
| State | Accepted |
| Headers | show |
Comments
On Tuesday, May 03, 2011 05:31:37 AM Shinya Kuribayashi wrote: > We need to make sure that all MIPS-based systems don't necessarily use > CP0 counter/compare registers as time keeping resources. And some MIPS > variant processors might come with different hardware specs with genuine > MIPS32 CP0 registers. Surprisingly, time.c works fine for us with our 64-bit OCTEON MIPS support, though I had to remove references to a global in the init code because DRAM isn't initialized at that point. The only file in lib we are not able to use is board.c. -Aaron
Patch
diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile index e315c1b..eb8e005 100644 --- a/arch/mips/cpu/mips32/Makefile +++ b/arch/mips/cpu/mips32/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).o START = start.o SOBJS-y = cache.o -COBJS-y = cpu.o interrupts.o +COBJS-y = cpu.o interrupts.o time.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/mips/lib/time.c b/arch/mips/cpu/mips32/time.c similarity index 100% rename from arch/mips/lib/time.c rename to arch/mips/cpu/mips32/time.c diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 4e90704..9244f31 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -33,7 +33,6 @@ COBJS-y += bootm_qemu_mips.o else COBJS-y += bootm.o endif -COBJS-y += time.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
Current timer routines (arch/mips/lib/timer.c) are implemented assuming that MIPS32 coprocessor (CP0) resources, Counter and Compare registers in this case, are available. But this doesn't always work. We need to make sure that all MIPS-based systems don't necessarily use CP0 counter/compare registers as time keeping resources. And some MIPS variant processors might come with different hardware specs with genuine MIPS32 CP0 registers. This patch makes each $(CPU) can have its own timer code. Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com> --- arch/mips/cpu/mips32/Makefile | 2 +- arch/mips/{lib => cpu/mips32}/time.c | 0 arch/mips/lib/Makefile | 1 - 3 files changed, 1 insertions(+), 2 deletions(-) rename arch/mips/{lib => cpu/mips32}/time.c (100%)