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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id 141-v6sm5014649pfu.167.2018.07.01.20.41.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 01 Jul 2018 20:41:35 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, marcus.shawcroft@arm.com, james.greenhalgh@arm.com Subject: [PATCH, aarch64 1/4] aarch64: Add movprfx alternatives for unpredicated patterns Date: Sun, 1 Jul 2018 20:41:30 -0700 Message-Id: <20180702034133.12511-2-rth@twiddle.net> In-Reply-To: <20180702034133.12511-1-rth@twiddle.net> References: <20180702034133.12511-1-rth@twiddle.net> X-IsSubscribed: yes * config/aarch64/aarch64.md (movprfx): New attr. (length): Default movprfx to 8. * config/aarch64/aarch64-sve.md (*mul3): Add movprfx alt. (*madd, *msubmul3_highpart): Likewise. (*3): Likewise. (*v3): Likewise. (*3): Likewise. (*3): Likewise. (*fma4, *fnma4): Likewise. (*fms4, *fnms4): Likewise. (*div4): Likewise. --- gcc/config/aarch64/aarch64-sve.md | 184 ++++++++++++++++++------------ gcc/config/aarch64/aarch64.md | 11 +- 2 files changed, 116 insertions(+), 79 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 8e2433385a8..3dee6a4376d 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -937,47 +937,53 @@ ;; to gain much and would make the instruction seem less uniform to the ;; register allocator. (define_insn "*mul3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (mult:SVE_I - (match_operand:SVE_I 2 "register_operand" "%0, 0") - (match_operand:SVE_I 3 "aarch64_sve_mul_operand" "vsm, w"))] + (match_operand:SVE_I 2 "register_operand" "%0, 0, w") + (match_operand:SVE_I 3 "aarch64_sve_mul_operand" "vsm, w, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ mul\t%0., %0., #%3 - mul\t%0., %1/m, %0., %3." + mul\t%0., %1/m, %0., %3. + movprfx\t%0, %2\;mul\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,*,yes")] ) (define_insn "*madd" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") (plus:SVE_I (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl, Upl") - (mult:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w") - (match_operand:SVE_I 3 "register_operand" "w, w"))] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (mult:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w"))] UNSPEC_MERGE_PTRUE) - (match_operand:SVE_I 4 "register_operand" "w, 0")))] + (match_operand:SVE_I 4 "register_operand" "w, 0, w")))] "TARGET_SVE" "@ mad\t%0., %1/m, %3., %4. - mla\t%0., %1/m, %2., %3." + mla\t%0., %1/m, %2., %3. + movprfx\t%0, %4\;mla\t%0., %1/m, %2., %3." + [(set_attr "movprfx" "*,*,yes")] ) (define_insn "*msub3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") (minus:SVE_I - (match_operand:SVE_I 4 "register_operand" "w, 0") + (match_operand:SVE_I 4 "register_operand" "w, 0, w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl, Upl") - (mult:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w") - (match_operand:SVE_I 3 "register_operand" "w, w"))] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (mult:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w, w") + (match_operand:SVE_I 3 "register_operand" "w, w, w"))] UNSPEC_MERGE_PTRUE)))] "TARGET_SVE" "@ msb\t%0., %1/m, %3., %4. - mls\t%0., %1/m, %2., %3." + mls\t%0., %1/m, %2., %3. + movprfx\t%0, %4\;mls\t%0., %1/m, %2., %3." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated highpart multiplication. @@ -997,15 +1003,18 @@ ;; Predicated highpart multiplication. (define_insn "*mul3_highpart" - [(set (match_operand:SVE_I 0 "register_operand" "=w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl") - (unspec:SVE_I [(match_operand:SVE_I 2 "register_operand" "%0") - (match_operand:SVE_I 3 "register_operand" "w")] + [(match_operand: 1 "register_operand" "Upl, Upl") + (unspec:SVE_I [(match_operand:SVE_I 2 "register_operand" "%0, w") + (match_operand:SVE_I 3 "register_operand" "w, w")] MUL_HIGHPART)] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" - "mulh\t%0., %1/m, %0., %3." + "@ + mulh\t%0., %1/m, %0., %3. + movprfx\t%0, %2\;mulh\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,yes")] ) ;; Unpredicated division. @@ -1025,17 +1034,19 @@ ;; Division predicated with a PTRUE. (define_insn "*3" - [(set (match_operand:SVE_SDI 0 "register_operand" "=w, w") + [(set (match_operand:SVE_SDI 0 "register_operand" "=w, w, ?&w") (unspec:SVE_SDI - [(match_operand: 1 "register_operand" "Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (SVE_INT_BINARY_SD:SVE_SDI - (match_operand:SVE_SDI 2 "register_operand" "0, w") - (match_operand:SVE_SDI 3 "aarch64_sve_mul_operand" "w, 0"))] + (match_operand:SVE_SDI 2 "register_operand" "0, w, w") + (match_operand:SVE_SDI 3 "aarch64_sve_mul_operand" "w, 0, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ \t%0., %1/m, %0., %3. - r\t%0., %1/m, %0., %2." + r\t%0., %1/m, %0., %2. + movprfx\t%0, %2\;\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated NEG, NOT and POPCOUNT. @@ -1222,17 +1233,19 @@ ;; or X isn't likely to gain much and would make the instruction seem ;; less uniform to the register allocator. (define_insn "*v3" - [(set (match_operand:SVE_I 0 "register_operand" "=w, w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (ASHIFT:SVE_I - (match_operand:SVE_I 2 "register_operand" "w, 0") - (match_operand:SVE_I 3 "aarch64_sve_shift_operand" "D, w"))] + (match_operand:SVE_I 2 "register_operand" "w, 0, w") + (match_operand:SVE_I 3 "aarch64_sve_shift_operand" "D, w, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ \t%0., %2., #%3 - \t%0., %1/m, %0., %3." + \t%0., %1/m, %0., %3. + movprfx\t%0, %2\;\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,*,yes")] ) ;; LSL, LSR and ASR by a scalar, which expands into one of the vector @@ -1723,14 +1736,17 @@ ;; Integer MIN/MAX predicated with a PTRUE. (define_insn "*3" - [(set (match_operand:SVE_I 0 "register_operand" "=w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl") - (MAXMIN:SVE_I (match_operand:SVE_I 2 "register_operand" "%0") - (match_operand:SVE_I 3 "register_operand" "w"))] + [(match_operand: 1 "register_operand" "Upl, Upl") + (MAXMIN:SVE_I (match_operand:SVE_I 2 "register_operand" "%0, w") + (match_operand:SVE_I 3 "register_operand" "w, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" - "\t%0., %1/m, %0., %3." + "@ + \t%0., %1/m, %0., %3. + movprfx\t%0, %2\;\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,yes")] ) ;; Unpredicated floating-point MIN/MAX. @@ -1749,14 +1765,17 @@ ;; Floating-point MIN/MAX predicated with a PTRUE. (define_insn "*3" - [(set (match_operand:SVE_F 0 "register_operand" "=w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl") - (FMAXMIN:SVE_F (match_operand:SVE_F 2 "register_operand" "%0") - (match_operand:SVE_F 3 "register_operand" "w"))] + [(match_operand: 1 "register_operand" "Upl, Upl") + (FMAXMIN:SVE_F (match_operand:SVE_F 2 "register_operand" "%0, w") + (match_operand:SVE_F 3 "register_operand" "w, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" - "fnm\t%0., %1/m, %0., %3." + "@ + fnm\t%0., %1/m, %0., %3. + movprfx\t%0, %2\;fnm\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,yes")] ) ;; Unpredicated fmin/fmax. @@ -1776,15 +1795,18 @@ ;; fmin/fmax predicated with a PTRUE. (define_insn "*3" - [(set (match_operand:SVE_F 0 "register_operand" "=w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl") - (unspec:SVE_F [(match_operand:SVE_F 2 "register_operand" "%0") - (match_operand:SVE_F 3 "register_operand" "w")] + [(match_operand: 1 "register_operand" "Upl, Upl") + (unspec:SVE_F [(match_operand:SVE_F 2 "register_operand" "%0, w") + (match_operand:SVE_F 3 "register_operand" "w, w")] FMAXMIN_UNS)] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" - "\t%0., %1/m, %0., %3." + "@ + \t%0., %1/m, %0., %3. + movprfx\t%0, %2\;\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated integer operations with select. @@ -2146,17 +2168,19 @@ ;; fma predicated with a PTRUE. (define_insn "*fma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w") - (match_operand:SVE_F 4 "register_operand" "w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0"))] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") + (match_operand:SVE_F 4 "register_operand" "w, w, w") + (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ fmad\t%0., %1/m, %4., %2. - fmla\t%0., %1/m, %3., %4." + fmla\t%0., %1/m, %3., %4. + movprfx\t%0, %2\;fmla\t%0., %1/m, %3., %4." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated fnma (%0 = (-%1 * %2) + %3). @@ -2177,18 +2201,20 @@ ;; fnma predicated with a PTRUE. (define_insn "*fnma4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w")) - (match_operand:SVE_F 4 "register_operand" "w, w") - (match_operand:SVE_F 2 "register_operand" "w, 0"))] + (match_operand:SVE_F 3 "register_operand" "%0, w, w")) + (match_operand:SVE_F 4 "register_operand" "w, w, w") + (match_operand:SVE_F 2 "register_operand" "w, 0, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ fmsb\t%0., %1/m, %4., %2. - fmls\t%0., %1/m, %3., %4." + fmls\t%0., %1/m, %3., %4. + movprfx\t%0, %2\;fmls\t%0., %1/m, %3., %4." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated fms (%0 = (%1 * %2) - %3). @@ -2209,18 +2235,20 @@ ;; fms predicated with a PTRUE. (define_insn "*fms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") - (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w") - (match_operand:SVE_F 4 "register_operand" "w, w") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (fma:SVE_F (match_operand:SVE_F 3 "register_operand" "%0, w, w") + (match_operand:SVE_F 4 "register_operand" "w, w, w") (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0")))] + (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ fnmsb\t%0., %1/m, %4., %2. - fnmls\t%0., %1/m, %3., %4." + fnmls\t%0., %1/m, %3., %4. + movprfx\t%0, %2\;fnmls\t%0., %1/m, %3., %4." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated fnms (%0 = (-%1 * %2) - %3). @@ -2242,19 +2270,21 @@ ;; fnms predicated with a PTRUE. (define_insn "*fnms4" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") (fma:SVE_F (neg:SVE_F - (match_operand:SVE_F 3 "register_operand" "%0, w")) - (match_operand:SVE_F 4 "register_operand" "w, w") + (match_operand:SVE_F 3 "register_operand" "%0, w, w")) + (match_operand:SVE_F 4 "register_operand" "w, w, w") (neg:SVE_F - (match_operand:SVE_F 2 "register_operand" "w, 0")))] + (match_operand:SVE_F 2 "register_operand" "w, 0, w")))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ fnmad\t%0., %1/m, %4., %2. - fnmla\t%0., %1/m, %3., %4." + fnmla\t%0., %1/m, %3., %4. + movprfx\t%0, %2\;fnmla\t%0., %1/m, %3., %4." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated floating-point division. @@ -2273,16 +2303,18 @@ ;; Floating-point division predicated with a PTRUE. (define_insn "*div3" - [(set (match_operand:SVE_F 0 "register_operand" "=w, w") + [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl") - (div:SVE_F (match_operand:SVE_F 2 "register_operand" "0, w") - (match_operand:SVE_F 3 "register_operand" "w, 0"))] + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (div:SVE_F (match_operand:SVE_F 2 "register_operand" "0, w, w") + (match_operand:SVE_F 3 "register_operand" "w, 0, w"))] UNSPEC_MERGE_PTRUE))] "TARGET_SVE" "@ fdiv\t%0., %1/m, %0., %3. - fdivr\t%0., %1/m, %0., %2." + fdivr\t%0., %1/m, %0., %2. + movprfx\t%0, %2\;fdiv\t%0., %1/m, %0., %3." + [(set_attr "movprfx" "*,*,yes")] ) ;; Unpredicated FNEG, FABS and FSQRT. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4ac6332a200..a014a012cc1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -251,9 +251,6 @@ ;; will be disabled when !TARGET_SVE. (define_attr "sve" "no,yes" (const_string "no")) -(define_attr "length" "" - (const_int 4)) - ;; Attribute that controls whether an alternative is enabled or not. ;; Currently it is only used to disable alternatives which touch fp or simd ;; registers when -mgeneral-regs-only is specified. @@ -277,6 +274,14 @@ ;; 1 :=: yes (define_attr "far_branch" "" (const_int 0)) +;; Attribute that specifies whether the alternative uses MOVPRFX. +(define_attr "movprfx" "no,yes" (const_string "no")) + +(define_attr "length" "" + (cond [(eq_attr "movprfx" "yes") + (const_int 8) + ] (const_int 4))) + ;; Strictly for compatibility with AArch32 in pipeline models, since AArch64 has ;; no predicated insns. (define_attr "predicated" "yes,no" (const_string "no"))