Submitted by Bernd Schmidt on May 3, 2011, 9:07 a.m.

Message ID | 4DBFC5D8.1090009@codesourcery.com |
---|---|

State | New |

Headers | show |

On 03/05/11 10:07, Bernd Schmidt wrote: > I tried to fix it with the patch below, which unfortunately doesn't work > since during combine we don't see the SIGN_EXTEND operations inside the > MULT, but two shift operations instead. Maybe you can complete it from here? I'll take a look. Thanks for the help! :) Andrew

Index: gcc/simplify-rtx.c =================================================================== --- gcc/simplify-rtx.c (revision 173242) +++ gcc/simplify-rtx.c (working copy) @@ -1000,6 +1000,23 @@ simplify_unary_operation_1 (enum rtx_cod && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF) return XEXP (op, 0); + /* Extending a widening multiplication should be canonicalized to + a wider widening multiplication. */ + if (GET_CODE (op) == MULT + && GET_CODE (XEXP (op, 0)) == SIGN_EXTEND + && GET_CODE (XEXP (op, 1)) == SIGN_EXTEND) + { + rtx op0 = XEXP (XEXP (op, 0), 0); + rtx op1 = XEXP (XEXP (op, 1), 0); + enum machine_mode op0_mode = GET_MODE (op0); + enum machine_mode op1_mode = GET_MODE (op1); + return simplify_gen_binary (MULT, mode, + simplify_gen_unary (SIGN_EXTEND, mode, + op0, op0_mode), + simplify_gen_unary (SIGN_EXTEND, mode, + op1, op1_mode)); + } + /* Check for a sign extension of a subreg of a promoted variable, where the promotion is sign-extended, and the target mode is the same as the variable's promotion. */ @@ -1071,6 +1088,23 @@ simplify_unary_operation_1 (enum rtx_cod && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))) return rtl_hooks.gen_lowpart_no_emit (mode, op); + /* Extending a widening multiplication should be canonicalized to + a wider widening multiplication. */ + if (GET_CODE (op) == MULT + && GET_CODE (XEXP (op, 0)) == ZERO_EXTEND + && GET_CODE (XEXP (op, 1)) == ZERO_EXTEND) + { + rtx op0 = XEXP (XEXP (op, 0), 0); + rtx op1 = XEXP (XEXP (op, 1), 0); + enum machine_mode op0_mode = GET_MODE (op0); + enum machine_mode op1_mode = GET_MODE (op1); + return simplify_gen_binary (MULT, mode, + simplify_gen_unary (ZERO_EXTEND, mode, + op0, op0_mode), + simplify_gen_unary (ZERO_EXTEND, mode, + op1, op1_mode)); + } + /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */ if (GET_CODE (op) == ZERO_EXTEND) return simplify_gen_unary (ZERO_EXTEND, mode, XEXP (op, 0),

`On 04/15/2011 12:54 PM, Andrew Stubbs wrote: > Ping. Trying to unblock this... I think the point is that both examples: long long foolong (long long x, short *a, short *b) { return x + (long long)*a * (long long)*b; } and long long foolong (long long x, short *a, short *b) { return x + *a * *b; } should produce the same code using the maddhidi pattern, and for that to happen, simplify_rtx must produce a canonical form of the 16->64 bit widening multiply. The form that already exists in arm.md looks better so we should pick that. I tried to fix it with the patch below, which unfortunately doesn't work since during combine we don't see the SIGN_EXTEND operations inside the MULT, but two shift operations instead. Maybe you can complete it from here? Bernd`