From patchwork Fri Jun 29 06:35:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 936642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="GP7gLTRc"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41H6P439LTz9s0n for ; Fri, 29 Jun 2018 16:36:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753261AbeF2GgX (ORCPT ); Fri, 29 Jun 2018 02:36:23 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:33911 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752967AbeF2GgX (ORCPT ); Fri, 29 Jun 2018 02:36:23 -0400 Received: by mail-lj1-f194.google.com with SMTP id l12-v6so6426432lja.1 for ; Thu, 28 Jun 2018 23:36:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a9ANTWX9cQYK2wSWMSEPRSJVL9id7DTDSn22l/2dqvQ=; b=GP7gLTRctfb6cKiO+SyJM8JfpjrvCE3u77mZDb5BKh0CtyFW98qN6RlVj8TUSekglS Us0YoHr18eotiov+G4k/kr+sNnpvqCAx8LtKMf75ULmA20jVX3M2NAYEwshFl/Bgg6tz ddQjNsAoWNU+ZWNrxJ2O2mQ0YId+ReVR76qBQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a9ANTWX9cQYK2wSWMSEPRSJVL9id7DTDSn22l/2dqvQ=; b=d3y5ZeWcPuPoqh+teICcFGwfQlu73mvqxyPuOHBnEmshP+a397zaTFG61RWQhU3X6T jOSL7GQiQ1HLaIWN/VppNqnM2HwFrSwdCX+a0jbBb282udCvgknAHvGYzxMWfcuDuvCU kRdFlNl28LKVEdwKFS87U6wjxn37X2/xAAmQaEwI5+M6bPY0x5onlMyhI6yW6CDbea/X w9t5Qy7XwYYita7iQrjKtbzj10wzx/F0FwYU9WBdIR3g/dELJMoOc+4J2ROYxtEDSOxk qMIlc5bPCELbYUyBF2j7I4nKZUhEVrwyishXVIKBBoYTJZzi+xeEwJkRvVZfHlpKZs9R 2CJg== X-Gm-Message-State: APt69E1feE6zdmj4JLnIQKP+6jk4urdgyaYf5ezlsNLIVsOTlGJ6t8hl ysTIPJX/dcrvCH6sO9z/Jd82v5g2l6A= X-Google-Smtp-Source: AAOMgpf7HKQLkbLfKHWfm01zfZ2/4n2QXeiF+7tK5K4PHNemYR4F3c2VNUbJpuVNkPefhtfJHhQssw== X-Received: by 2002:a2e:141e:: with SMTP id u30-v6mr9492398ljd.134.1530254181470; Thu, 28 Jun 2018 23:36:21 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id v2-v6sm1382162ljj.71.2018.06.28.23.36.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 23:36:20 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Alessandro Rubini , Bartosz Golaszewski Subject: [PATCH 15/18] gpio: sta2x11: Inline regs macro Date: Fri, 29 Jun 2018 08:35:41 +0200 Message-Id: <20180629063544.3826-15-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180629063544.3826-1-linus.walleij@linaro.org> References: <20180629063544.3826-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org I don't like the __namespace and this is simple enough to just inline at all sites. Cc: Alessandro Rubini Cc: Bartosz Golaszewski Signed-off-by: Linus Walleij Acked-by: Alessandro Rubini --- drivers/gpio/gpio-sta2x11.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-sta2x11.c b/drivers/gpio/gpio-sta2x11.c index 4af90968e838..2283c869ad5d 100644 --- a/drivers/gpio/gpio-sta2x11.c +++ b/drivers/gpio/gpio-sta2x11.c @@ -59,11 +59,6 @@ struct gsta_gpio { unsigned irq_type[GSTA_NR_GPIO]; }; -static inline struct gsta_regs __iomem *__regs(struct gsta_gpio *chip, int nr) -{ - return chip->regs[nr / GSTA_GPIO_PER_BLOCK]; -} - /* * gpio methods */ @@ -71,7 +66,7 @@ static inline struct gsta_regs __iomem *__regs(struct gsta_gpio *chip, int nr) static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) { struct gsta_gpio *chip = gpiochip_get_data(gpio); - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); if (val) @@ -83,7 +78,7 @@ static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr) { struct gsta_gpio *chip = gpiochip_get_data(gpio); - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); return !!(readl(®s->dat) & bit); @@ -93,7 +88,7 @@ static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, int val) { struct gsta_gpio *chip = gpiochip_get_data(gpio); - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); writel(bit, ®s->dirs); @@ -108,7 +103,7 @@ static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) { struct gsta_gpio *chip = gpiochip_get_data(gpio); - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); writel(bit, ®s->dirc); @@ -161,7 +156,7 @@ static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */ */ static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg) { - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; unsigned long flags; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); u32 val; @@ -230,7 +225,7 @@ static void gsta_irq_disable(struct irq_data *data) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); struct gsta_gpio *chip = gc->private; int nr = data->irq - chip->irq_base; - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); u32 val; unsigned long flags; @@ -253,7 +248,7 @@ static void gsta_irq_enable(struct irq_data *data) struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); struct gsta_gpio *chip = gc->private; int nr = data->irq - chip->irq_base; - struct gsta_regs __iomem *regs = __regs(chip, nr); + struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK]; u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK); u32 val; int type;