From patchwork Fri Jun 29 06:35:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 936636 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="XAkdyaN/"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41H6Nq1c4Bz9s0w for ; Fri, 29 Jun 2018 16:36:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753211AbeF2GgK (ORCPT ); Fri, 29 Jun 2018 02:36:10 -0400 Received: from mail-lj1-f194.google.com ([209.85.208.194]:36784 "EHLO mail-lj1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752971AbeF2GgK (ORCPT ); Fri, 29 Jun 2018 02:36:10 -0400 Received: by mail-lj1-f194.google.com with SMTP id o26-v6so6405231ljg.3 for ; Thu, 28 Jun 2018 23:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q85ETMV7uWzWnrx6g87lbPcFrUcB3P+KFmPAfKIywE0=; b=XAkdyaN/3Fgiz74JHpNy4gd+vkbFoeLXfs4dblxaCQIzHaik7h5ci15eWjWKvrkm7R JbGr4Ggvl4B6aXgig0snOSOqLYr1KhA/7gmr6Oti8xK17htpazfI5wr+0/iGxp5yRN9t 2cdQSl/K7hVodMiB4ghidySQSrmhpHd4U83s4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q85ETMV7uWzWnrx6g87lbPcFrUcB3P+KFmPAfKIywE0=; b=AJWxd610gl8CC6bZz5xquNUamZCig+tz8vrDo+XySEHWXPYuQ2GQG6SeyBYCiblTnU d2wBWMFvHBTKI5IYjAKTnkhM+6cKoSVyhPDjZrleY0rqr7zrf7t6lQqWqpUIDsOAlAZI i4dH7odd8qgxYWezSFxV2XzqbMVgGB6x2NfT6W+Ab+QCeFQsMwN5XOzaD1QRodNXP7jf m2i6zERhhkzmBFnAMG6vsUumLv/yqRpES/Ga+idYEryRjIx5upuOykSDDdAANjqe60nn PqlNcHDLNT0+6nJUpgZ7c0AfpHv11H/P8XMGaYz2jsw9Sf3lxIZinoJMoLsRTU4UFlis J3CQ== X-Gm-Message-State: APt69E3nwBuzXYGDjIgPaFwD9nXQYl33Us/SYM99vFUCneVRDwWilzsI WBMOhSPOhejRP7T/3v6fdfSg31O+6sk= X-Google-Smtp-Source: AAOMgpdN9GEQjLRO5VMvWyz34T8VWuUtJrcCEynheU9QgVVnO0TokvQzKfDvem7pNcfj+4u1BcRiXw== X-Received: by 2002:a2e:20e8:: with SMTP id g101-v6mr8958833lji.100.1530254168399; Thu, 28 Jun 2018 23:36:08 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id v2-v6sm1382162ljj.71.2018.06.28.23.36.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Jun 2018 23:36:07 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij , Bruno Randolf Subject: [PATCH 09/18] gpio: sch311x: Use RMW to change direction Date: Fri, 29 Jun 2018 08:35:35 +0200 Message-Id: <20180629063544.3826-9-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180629063544.3826-1-linus.walleij@linaro.org> References: <20180629063544.3826-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Bit 0 in the config register obviously controls the direction of the GPIO so instead of hammering 0x0/0x1 into that register, use read-modify-write so that we can also alter the other bits in the register. Cc: Bruno Randolf Signed-off-by: Linus Walleij --- drivers/gpio/gpio-sch311x.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpio/gpio-sch311x.c b/drivers/gpio/gpio-sch311x.c index ed64f7fa23b1..faf44178f97b 100644 --- a/drivers/gpio/gpio-sch311x.c +++ b/drivers/gpio/gpio-sch311x.c @@ -23,10 +23,9 @@ #define DRV_NAME "gpio-sch311x" -#define SCH311X_GPIO_CONF_OUT 0x00 -#define SCH311X_GPIO_CONF_IN 0x01 -#define SCH311X_GPIO_CONF_INVERT 0x02 -#define SCH311X_GPIO_CONF_OPEN_DRAIN 0x80 +#define SCH311X_GPIO_CONF_DIR BIT(0) +#define SCH311X_GPIO_CONF_INVERT BIT(1) +#define SCH311X_GPIO_CONF_OPEN_DRAIN BIT(7) #define SIO_CONFIG_KEY_ENTER 0x55 #define SIO_CONFIG_KEY_EXIT 0xaa @@ -196,10 +195,12 @@ static void sch311x_gpio_set(struct gpio_chip *chip, unsigned offset, static int sch311x_gpio_direction_in(struct gpio_chip *chip, unsigned offset) { struct sch311x_gpio_block *block = gpiochip_get_data(chip); + unsigned char data; spin_lock(&block->lock); - outb(SCH311X_GPIO_CONF_IN, block->runtime_reg + - block->config_regs[offset]); + data = inb(block->runtime_reg + block->config_regs[offset]); + data |= SCH311X_GPIO_CONF_DIR; + outb(data, block->runtime_reg + block->config_regs[offset]); spin_unlock(&block->lock); return 0; @@ -209,12 +210,13 @@ static int sch311x_gpio_direction_out(struct gpio_chip *chip, unsigned offset, int value) { struct sch311x_gpio_block *block = gpiochip_get_data(chip); + unsigned char data; spin_lock(&block->lock); - outb(SCH311X_GPIO_CONF_OUT, block->runtime_reg + - block->config_regs[offset]); - + data = inb(block->runtime_reg + block->config_regs[offset]); + data &= ~SCH311X_GPIO_CONF_DIR; + outb(data, block->runtime_reg + block->config_regs[offset]); __sch311x_gpio_set(block, offset, value); spin_unlock(&block->lock); @@ -230,7 +232,7 @@ static int sch311x_gpio_get_direction(struct gpio_chip *chip, unsigned offset) data = inb(block->runtime_reg + block->config_regs[offset]); spin_unlock(&block->lock); - return !!(data & SCH311X_GPIO_CONF_IN); + return !!(data & SCH311X_GPIO_CONF_DIR); } static int sch311x_gpio_probe(struct platform_device *pdev)