[U-Boot,2/3] dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards

Message ID	1530156197-7770-2-git-send-email-ye.li@nxp.com
State	Awaiting Upstream
Delegated to:	Stefano Babic
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Ye Li <ye.li@nxp.com> To: sbabic@denx.de, peng.fan@nxp.com, ashish.kumar@nxp.com, fabio.estevam@nxp.com Date: Wed, 27 Jun 2018 20:23:16 -0700 Message-Id: <1530156197-7770-2-git-send-email-ye.li@nxp.com> In-Reply-To: <1530156197-7770-1-git-send-email-ye.li@nxp.com> References: <1530156197-7770-1-git-send-email-ye.li@nxp.com> MIME-Version: 1.0 Received-SPF: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DB7PR04MB5306; 23:Rwp+lCHOha8E97sgoqH1ADqVCLKovq/dot3ZjmPqi?= kDJ73z9L1m4QilhDftrclKjgPuSt5pXMtDmkbZWztjaCfzFHsNpz8CRI8cf/ee5VEo7vT2igdIsUWZon/6wLzTq0Jol6ekxGug9grfiQLtiTNaLwVhcrp6YoZD7oqYrYE2ATcrbeKpKopg0gmn5LcG2wfhbLsRfuZTfR1BITs5WvgjKqhXVlaHiqirW/dm8rtlkD0NG/1LS5nWZhWVSkMG61FhX4i8jJbcf/mA30Nz4/NIuFj79X6iPyBPOhpQmmE6OD32O0iAp5yRpxmAFMJBatI0KBKFgx2fnMJgJv8CIy5pu1qjgYbqEFL3sWug1UETB7w+BTJo4fAI0QjCg0GXGY2eYBso7mp39wGGBzONDc1RwCtyYachLqQq71VJUhRFvmUdIZ4PIr0zL6O4AojPWLS/AHcMJYULyc4+NnPRrOy2gbom2VyC+YqXkNQMhO1oETJP7JRJJJCEhz5b2vBa64hbfCenLXfgU+oZ+lcVYlTpTvqZMk+zIbX7IIyqns7GUKelnSXHZ1rG2BgeidogVztqD9jkie79RRT9tCdo9l6bZjI8vWNwn/PlRXFmo16mWdNFvSMjZ0sFp9JGGF3sEuIygw5IKtsYjiMdBvy1BXw/r3lwacbiqBJEt/8Fv55ft8UZtWS/FT2Mib5htMHqGg9PujR1eK6CDEb+kZk03fxRCVv623HQGpLrbMPub8Y5eNA+JGC7ijlHb/fm1x8+3L+VsSQ7qmk9V/JjDPLVOtN+I5ztYaCRsLmrqrg7XEFraZs/0E+VJarE2HVCR7pme/M0Chz+bJbeuiRVp2WiOUGjOXPMxhZeYpb7dVSuQpJ//3Pb3iXEXzjdyymYzzLcvvjDVUia2h4YJlHGiPjrd15NmWu/anaq5f0J9/cNzkjdr5T5vSQi51ZuTSmtAs5lB8NIwb8QPsjDhoV5WU5IwiSY5XTa+M/ZdbMKQz/ERrW0K/AYlf9yanYg5HC0REHs+3W9SS5Ug8bdIhmO5w5mPK0rqs8zzP6KHn/IbsoVN0pMTHXLOn8/miDtDccoa6uIT7hxbUzTmJDYX2J3Y2dCvIu3+HsCTj8HICBLbY0/X/xxrsO8WhZo+3rgZ4TR5yVu0D3GyyKoEdHzwEOiEntMH5iGgsf2rBpD/aKKCxKC7fZ9gccOQcSJf0VAseZ6gm+dGuHfSwNmFlgLhIgKvUkq65UC0TazYsFLLp8iBA8Ou2F1spX5k21oQ1mCTHNeeTZFS X-Microsoft-Antispam-Message-Info: hGImSy7yV2i/GHKHsijkuk3wMDnRCJ8oHXmebhRTjHRRrHjgvTcOp/ECmMyMg0KkX1Qoe1GvUd93EdwrFNBUut0Y2RCj88haKEiHEIiAJagIu2xQ04av76v6OJWLeLAO3LQ1idRQeb6qRag1Wli0/HxwGfWcdN0mP32TpJKLMM1rWlqBRzHFzVasANNbMkM9Y/CtgxFoS7X/gD1St7tbhO1KBtjOsCnVzuv0y8QUHhfK1S23WzKF4ZYz9EYwelUelOUuTQooC7+Y0+bdnpC2937JurlYxCfdhNRy9swGbxZTp1w/m/CddrVS+UoHTm1lAOpXirqCiKFcyi2TdReDkwIOLw7W8QUfiHhc+SdjhcQ= X-Microsoft-Exchange-Diagnostics: 1; DB7PR04MB5306; 6:nhy7gfj9t9LVuhTuWJTIb6M6vb9rhRi5J422o7RlIyOFY3CMdCiLcT0CBtt+E4j+061WR3htBDIzzJqSih6XcZ6zwA6uzE+SBaFPkjlprTrQfBUJQzzl4j8RWOyb7Z/K2O1DoTrBKSUvO161ZIDOyc/MTjjUOjwGznBW8vNyOUI4aDhukhLsmlsyiWOTfN4zVDNyM7jtUFaLWAvPTLlrTQ+upZ/U2jw0cX+/jkkrjFK2w0DcQ8KSXxNdYfUJ/tU9ZM3TDJ/0pG9Wcc1h71w4J+iWZj095Nf27xWsSQ4quq2/VfI4C/37Hz8p1ZbDRHtT/7UM/9dGsUgmF7h/PSWX2Yp+IyUG/DrfHd7CRczUxTPvRylh0w7EbcpWBvO07IYCQJPLhbv2WqbSY4TX5SktdWogdxGpRqDJ99pZGgX9hiSk6w9K0dUe5swjJ63zGMmMeq2OKpFyPQweSLWhX4JLVQ==; 5:ZJGO+fsBBbwLjpdXCV25ez+xCatZpbRYkTjFpoaRzuabXDtcqIirTMTffzE1xLZPKB+o+OQGLrXJaASGTRNAgofQ8xVZKPqBrMMlZfCr52gT4djoKecISd+MpxJiEZn+wCZ+gXMJX9SpJGDj5+PbZWox6pvd57l4uj18lHTGLw8=; 24:WHXUvd7jjnU/3DbyNs2htAidH9uFJ1klGO9z5zgVijInHLMwqSJo97+dbhXIJC67um0X4S/aWXmD8R4akWiSFuZ7za09PZoQ7eVHhDInpF0= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DB7PR04MB5306; 7:PK8LtDviKFXd3Ynb9rltZIcYNuL0yn2jvxdMMajHegMPR+3r1ZnIvyyL1QAdry7h4ebR6NPhvHc0izh+RyiDuf5rohaUCVP6dvDJfSm1mB2OdCYPqHEGvrpgmxv1oQ2aeDc4zb09LBbHHzZZLC9kHPNN/s6bi005pBsEUGmnd9Rijyk3G7UB/Ude3MxCbCG1CytjnQhr2vKeaFiyp855+Tt5HGaixDfAhYvICLTiLTFTKZPpeokJ5rJ77tFENM6g Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/3] dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	[U-Boot,1/3] dts: imx6ul: Update alias to support DM \| expand [U-Boot,1/3] dts: imx6ul: Update alias to support DM [U-Boot,2/3] dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards [U-Boot,3/3] imx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dfabec0..7eeb7ed 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -428,7 +428,9 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-geam-kit.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ - imx6ul-opos6uldev.dtb + imx6ul-opos6uldev.dtb \ + imx6ul-14x14-evk.dtb \ + imx6ul-9x9-evk.dtb dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi new file mode 100644 index 0000000..db640d6 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi { + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6ul-14x14-evk.dts b/arch/arm/dts/imx6ul-14x14-evk.dts new file mode 100644 index 0000000..a642d77 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; + + aliases { + spi5 = &soft_spi; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + soft_spi: soft-spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <&ethphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <&ethphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&reg_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi new file mode 100644 index 0000000..db640d6 --- /dev/null +++ b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi { + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts new file mode 100644 index 0000000..2270451 --- /dev/null +++ b/arch/arm/dts/imx6ul-9x9-evk.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; + + aliases { + spi5 = &soft_spi; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay = <20000>; + enable-active-high; + }; + }; + + soft_spi: soft-spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <&ethphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <&ethphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <&reg_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +};

[U-Boot,2/3] dts: imx6ul_evk: Add DTS files for 14x14 EVK and 9x9 EVK boards

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Patch