From patchwork Fri Apr 29 21:49:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timur Tabi X-Patchwork-Id: 93483 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1F396B6F65 for ; Sat, 30 Apr 2011 07:50:35 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0959F2808D; Fri, 29 Apr 2011 23:50:26 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hwmELeDdg6e8; Fri, 29 Apr 2011 23:50:25 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D5CA628090; Fri, 29 Apr 2011 23:50:18 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9E91D28090 for ; Fri, 29 Apr 2011 23:50:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pN5gLe4wk1vW for ; Fri, 29 Apr 2011 23:50:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from TX2EHSOBE002.bigfish.com (tx2ehsobe001.messaging.microsoft.com [65.55.88.11]) by theia.denx.de (Postfix) with ESMTPS id 273E62808D for ; Fri, 29 Apr 2011 23:50:05 +0200 (CEST) Received: from mail154-tx2-R.bigfish.com (10.9.14.254) by TX2EHSOBE002.bigfish.com (10.9.40.22) with Microsoft SMTP Server id 14.1.225.8; Fri, 29 Apr 2011 21:50:01 +0000 Received: from mail154-tx2 (localhost.localdomain [127.0.0.1]) by mail154-tx2-R.bigfish.com (Postfix) with ESMTP id 29DD91B2876F for ; Fri, 29 Apr 2011 21:50:01 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail154-tx2 (localhost.localdomain [127.0.0.1]) by mail154-tx2 (MessageSwitch) id 1304113800995419_9618; Fri, 29 Apr 2011 21:50:00 +0000 (UTC) Received: from TX2EHSMHS029.bigfish.com (unknown [10.9.14.248]) by mail154-tx2.bigfish.com (Postfix) with ESMTP id F09AE3E0050 for ; Fri, 29 Apr 2011 21:50:00 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS029.bigfish.com (10.9.99.129) with Microsoft SMTP Server (TLS) id 14.1.225.8; Fri, 29 Apr 2011 21:50:00 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.270.2; Fri, 29 Apr 2011 16:49:59 -0500 Received: from efes.am.freescale.net (efes.am.freescale.net [10.82.123.3]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p3TLnxRn022654; Fri, 29 Apr 2011 16:49:59 -0500 (CDT) From: Timur Tabi To: , Date: Fri, 29 Apr 2011 16:49:58 -0500 Message-ID: <1304113798-6655-1-git-send-email-timur@freescale.com> X-Mailer: git-send-email 1.7.3.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH] [v3] powerpc/85xx: fix compatible property for the L2 cache node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The compatible property for the L2 cache node (on 85xx systems that don't have a CPC) was using a value for the property length that did not match the actual length of the property. Signed-off-by: Timur Tabi --- arch/powerpc/cpu/mpc85xx/fdt.c | 20 ++++++++++++-------- 1 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 642f6c5..6d264e7 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -165,7 +165,6 @@ static inline void ft_fixup_l2cache(void *blob) int len, off; u32 *ph; struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); - char compat_buf[38]; const u32 line_size = 32; const u32 num_ways = 8; @@ -192,22 +191,27 @@ static inline void ft_fixup_l2cache(void *blob) } if (cpu) { + char buf[40]; + if (isdigit(cpu->name[0])) - len = sprintf(compat_buf, - "fsl,mpc%s-l2-cache-controller", cpu->name); + /* MPCxxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,mpc%s-l2-cache-controller", + cpu->name) + 1; else - len = sprintf(compat_buf, - "fsl,%c%s-l2-cache-controller", - tolower(cpu->name[0]), cpu->name + 1); + /* Pxxxx or Txxxx, where xxxx == 4-digit number */ + len = sprintf(buf, "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1) + 1; + + /* append "cache" to the string */ + len += sprintf(buf + len + 1, "cache") + 1; - sprintf(&compat_buf[len + 1], "cache"); + fdt_setprop(blob, off, "compatible", buf, len); } fdt_setprop(blob, off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, off, "cache-block-size", line_size); fdt_setprop_cell(blob, off, "cache-size", size); fdt_setprop_cell(blob, off, "cache-sets", num_sets); fdt_setprop_cell(blob, off, "cache-level", 2); - fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); /* we dont bother w/L3 since no platform of this type has one */ }