Patchwork [21/33] target-alpha: Disable interrupts properly.

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Submitter Richard Henderson
Date April 28, 2011, 8:51 p.m.
Message ID <1304023875-25040-22-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/93331/
State New
Headers show

Comments

Richard Henderson - April 28, 2011, 8:51 p.m.
Interrupts are disabled in PALmode, and when the PS IL is high enough.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 cpu-exec.c          |   28 +++++++++++++++++++++++++---
 target-alpha/exec.h |   11 ++++++++++-
 2 files changed, 35 insertions(+), 4 deletions(-)

Patch

diff --git a/cpu-exec.c b/cpu-exec.c
index e1b85d6..f22ac7f 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -532,9 +532,31 @@  int cpu_exec(CPUState *env1)
                         next_tb = 0;
                     }
 #elif defined(TARGET_ALPHA)
-                    if (interrupt_request & CPU_INTERRUPT_HARD) {
-                        do_interrupt(env);
-                        next_tb = 0;
+                    {
+                        int idx = -1;
+                        /* ??? This hard-codes the OSF/1 interrupt levels.  */
+		        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
+                        case 0 ... 3:
+                            if (interrupt_request & CPU_INTERRUPT_HARD) {
+                                idx = EXCP_DEV_INTERRUPT;
+                            }
+                            /* FALLTHRU */
+                        case 4:
+                            if (interrupt_request & CPU_INTERRUPT_TIMER) {
+                                idx = EXCP_CLK_INTERRUPT;
+                            }
+                            /* FALLTHRU */
+                        case 5:
+                            if (interrupt_request & CPU_INTERRUPT_SMI) {
+                                idx = EXCP_SMP_INTERRUPT;
+                            }
+                        }
+                        if (idx >= 0) {
+                            env->exception_index = idx;
+                            env->error_code = 0;
+                            do_interrupt(env);
+                            next_tb = 0;
+                        }
                     }
 #elif defined(TARGET_CRIS)
                     if (interrupt_request & CPU_INTERRUPT_HARD
diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 6ae96d1..adf835e 100644
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -39,7 +39,16 @@  register struct CPUAlphaState *env asm(AREG0);
 
 static inline int cpu_has_work(CPUState *env)
 {
-    return (env->interrupt_request & CPU_INTERRUPT_HARD);
+    /* Here we are checking to see if the CPU should wake up from HALT.
+       We will have gotten into this state only for WTINT from PALmode.  */
+    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+       asleep even if (some) interrupts have been asserted.  For now, 
+       assume that if a CPU really wants to stay asleep, it will mask
+       interrupts at the chipset level, which will prevent these bits
+       from being set in the first place.  */
+    return env->interrupt_request & (CPU_INTERRUPT_HARD
+                                     | CPU_INTERRUPT_TIMER
+                                     | CPU_INTERRUPT_SMI);
 }
 
 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)