From patchwork Thu Apr 28 20:50:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0725EB6FBF for ; Fri, 29 Apr 2011 07:01:14 +1000 (EST) Received: from localhost ([::1]:39508 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYKl-0005tr-BH for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 17:01:11 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBY-0005Fv-Aa for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBW-0005bj-Uz for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:40 -0400 Received: from mail-px0-f179.google.com ([209.85.212.179]:45275) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBW-0005Xx-Nb for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:38 -0400 Received: by mail-px0-f179.google.com with SMTP id 2so298075pxi.10 for ; Thu, 28 Apr 2011 13:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=XgDrR3UObp3aaUWfdYMy3xxMTHw0pbFg9/2Ew/5bC+k=; b=vNSuVv4fAdAXPvk+1+WIe6XRCgAu845DejLD6NvFX1HJcJ9lG/olFXxOhAFz2QTnP+ M6SRRSNUXjvIoc8+OBBazVbDRiA9N3Y0k4MXDSRj1ozJmqkEaeJQAW0e/NEtA54Pf5nU fmnx20evbjlDbZNsVB51SP5cXM6lJG2pKSR6M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=jr7skTKxYaeFiPq7nP8MJsfsr+XnRHH4Qk60wWPEoYGODrGIGm9bcfeQ9watjQtN2D tSs/LHl7lZO8KHF68105CeTXYooNYKxCB3WaU1NEPcE8vAJ4EmAmj7xFaAwzNRez8YDU YCIi+q4xDGIWucl36h1efEc6RFws2ebTZyb1E= Received: by 10.142.178.17 with SMTP id a17mr1316292wff.65.1304023898238; Thu, 28 Apr 2011 13:51:38 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.36 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:50:54 -0700 Message-Id: <1304023875-25040-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.212.179 Subject: [Qemu-devel] [PATCH 12/33] target-alpha: Add IPRs to be used by the emulation PALcode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These aren't actually used yet, but we can at least access them via the HW_MFPR and HW_MTPR instructions. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 13 +++++++ target-alpha/translate.c | 87 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 98 insertions(+), 2 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 60b753f..60445dc 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -247,6 +247,7 @@ struct CPUAlphaState { uint8_t intr_flag; uint8_t fen; uint8_t pal_mode; + uint32_t pcc_ofs; /* These pass data from the exception logic in the translator and helpers to the OS entry point. This is used for both system @@ -255,6 +256,18 @@ struct CPUAlphaState { uint64_t trap_arg1; uint64_t trap_arg2; +#if !defined(CONFIG_USER_ONLY) + /* The internal data required by our emulation of the Unix PALcode. */ + uint64_t exc_addr; + uint64_t palbr; + uint64_t ptbr; + uint64_t vptptr; + uint64_t sysval; + uint64_t usp; + uint64_t shadow[8]; + uint64_t scratch[24]; +#endif + #if TARGET_LONG_BITS > HOST_LONG_BITS /* temporary fixed-point registers * used to emulate 64 bits target on 32 bits hosts diff --git a/target-alpha/translate.c b/target-alpha/translate.c index b14b8fc..9e1576d 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1468,6 +1468,89 @@ static void gen_rx(int ra, int set) tcg_temp_free_i32(tmp); } +#ifndef CONFIG_USER_ONLY + +#define PR_BYTE 0x100000 +#define PR_LONG 0x200000 + +static int cpu_pr_data(int pr) +{ + switch (pr) { + case 0: return offsetof(CPUAlphaState, ps) | PR_BYTE; + case 1: return offsetof(CPUAlphaState, fen) | PR_BYTE; + case 2: return offsetof(CPUAlphaState, pcc_ofs) | PR_LONG; + case 3: return offsetof(CPUAlphaState, trap_arg0); + case 4: return offsetof(CPUAlphaState, trap_arg1); + case 5: return offsetof(CPUAlphaState, trap_arg2); + case 6: return offsetof(CPUAlphaState, exc_addr); + case 7: return offsetof(CPUAlphaState, palbr); + case 8: return offsetof(CPUAlphaState, ptbr); + case 9: return offsetof(CPUAlphaState, vptptr); + case 10: return offsetof(CPUAlphaState, unique); + case 11: return offsetof(CPUAlphaState, sysval); + case 12: return offsetof(CPUAlphaState, usp); + + case 32 ... 39: + return offsetof(CPUAlphaState, shadow[pr - 32]); + case 40 ... 63: + return offsetof(CPUAlphaState, scratch[pr - 40]); + } + return 0; +} + +static void gen_mfpr(int ra, int regno) +{ + int data = cpu_pr_data(regno); + + /* In our emulated PALcode, these processor registers have no + side effects from reading. */ + if (ra == 31) { + return; + } + + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + if (data == 0) { + tcg_gen_movi_i64(cpu_ir[ra], 0); + } else if (data & PR_BYTE) { + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_ld32s_i64(cpu_ir[ra], cpu_env, data & ~PR_LONG); + } else { + tcg_gen_ld_i64(cpu_ir[ra], cpu_env, data); + } +} + +static void gen_mtpr(int rb, int regno) +{ + TCGv tmp; + int data; + + if (rb == 31) { + tmp = tcg_const_i64(0); + } else { + tmp = cpu_ir[rb]; + } + + /* The basic registers are data only, and unknown registers + are read-zero, write-ignore. */ + data = cpu_pr_data(regno); + if (data != 0) { + if (data & PR_BYTE) { + tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); + } else if (data & PR_LONG) { + tcg_gen_st32_i64(tmp, cpu_env, data & ~PR_LONG); + } else { + tcg_gen_st_i64(tmp, cpu_env, data); + } + } + + if (rb == 31) { + tcg_temp_free(tmp); + } +} +#endif /* !USER_ONLY*/ + static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) { uint32_t palcode; @@ -2580,7 +2663,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - tcg_abort(); + gen_mfpr(ra, insn & 0xffff); break; #endif case 0x1A: @@ -2856,7 +2939,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - abort(); + gen_mtpr(rb, insn & 0xffff); break; #endif case 0x1E: