From patchwork Thu Apr 28 20:51:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93323 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 867F4B6F62 for ; Fri, 29 Apr 2011 07:01:09 +1000 (EST) Received: from localhost ([::1]:39251 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYKf-0005lC-Ht for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 17:01:05 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBt-0005qy-0b for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:52:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBr-0005hx-JW for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:52:00 -0400 Received: from mail-px0-f179.google.com ([209.85.212.179]:45275) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBr-0005Xx-Dg for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:59 -0400 Received: by mail-px0-f179.google.com with SMTP id 2so298075pxi.10 for ; Thu, 28 Apr 2011 13:51:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=AYPsZkokv9Fyn6GPg4tZ/JdiXQiDfClcjMz+1stxOAc=; b=jm6Xu6jVfQfUQjz60i/WzJrET4g8XxBEXKp107HhvGFf0uCTGdhrOXSYT6rtKJrNlW R1uWCt99Xu6Ivx96BRsaqnehQagLYnn/HewlqZR/PQhnc8U5iVcqMDoa/V4mJcZfm2Sv 0kQ1uYiJmNTU7ILyGfgyVuG8Rg33gXiBNBWkQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=dycc8g5f0R8Xf6TR/JnYHBW+Ho6PuHOhkWRHJrAGs/G48GcpXT3w7yvywIJ5RZB6LJ K1rGXsMNSgYTq07qBDysFLMuKSGzRg5YF+ifbfKTbKGrwctKsJ77qg6gmh+Jwr5o1KAT Zb2nJSug6bvV8u1cNpNj0HTutCNsQtEm/oJs8= Received: by 10.142.196.12 with SMTP id t12mr1289358wff.449.1304023918579; Thu, 28 Apr 2011 13:51:58 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.57 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:51:13 -0700 Message-Id: <1304023875-25040-32-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.212.179 Subject: [Qemu-devel] [PATCH 31/33] target-alpha: Implement WAIT IPR. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org --- target-alpha/translate.c | 31 +++++++++++++++++++++---------- 1 files changed, 21 insertions(+), 10 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 8107d19..7b976be 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1621,9 +1621,10 @@ static void gen_mfpr(int ra, int regno) } } -static void gen_mtpr(int rb, int regno) +static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) { TCGv tmp; + int data; if (rb == 31) { tmp = tcg_const_i64(0); @@ -1631,19 +1632,27 @@ static void gen_mtpr(int rb, int regno) tmp = cpu_ir[rb]; } - /* These two register numbers perform a TLB cache flush. Thankfully we - can only do this inside PALmode, which means that the current basic - block cannot be affected by the change in mappings. */ - if (regno == 255) { + switch (regno) { + case 255: /* TBIA */ gen_helper_tbia(); - } else if (regno == 254) { + break; + + case 254: /* TBIS */ gen_helper_tbis(tmp); - } else { + break; + + case 253: + /* WAIT */ + tmp = tcg_const_i64(1); + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted)); + return gen_excp(ctx, EXCP_HLT, 0); + + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ - int data = cpu_pr_data(regno); + data = cpu_pr_data(regno); if (data != 0) { if (data & PR_BYTE) { tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE); @@ -1653,11 +1662,14 @@ static void gen_mtpr(int rb, int regno) tcg_gen_st_i64(tmp, cpu_env, data); } } + break; } if (rb == 31) { tcg_temp_free(tmp); } + + return NO_EXIT; } #endif /* !USER_ONLY*/ @@ -3052,8 +3064,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) /* HW_MTPR (PALcode) */ #ifndef CONFIG_USER_ONLY if (ctx->tb->flags & TB_FLAGS_PAL_MODE) { - gen_mtpr(rb, insn & 0xffff); - break; + return gen_mtpr(ctx, rb, insn & 0xffff); } #endif goto invalid_opc;