From patchwork Thu Apr 28 20:50:57 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 93311 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 49C35100A24 for ; Fri, 29 Apr 2011 06:56:23 +1000 (EST) Received: from localhost ([::1]:41621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYG4-0005XH-O8 for incoming@patchwork.ozlabs.org; Thu, 28 Apr 2011 16:56:20 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBb-0005Lv-Tw for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFYBa-0005dA-6k for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:43 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:41034) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFYBZ-0005Xk-VB for qemu-devel@nongnu.org; Thu, 28 Apr 2011 16:51:42 -0400 Received: by mail-pz0-f45.google.com with SMTP id 30so2296231pzk.4 for ; Thu, 28 Apr 2011 13:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=+oCboOF2xsUjSaLHXtV9nZggJxdt6iInVLs5FxJNidM=; b=hsMuLF2wMxwWXCVE/H6S+ccHSX7xuW4c3Uz8a2efRsMSDKq7fEgy45AxaXbjAU07UL MPRxFi9EamWNRE19ppieyTeh0zEb8wzdXTzCxYs5b5/Qf+tfLmRujgr4b0trXPotPoDk UPL+9KbOVndFUuTi+oG6SI7wSFVePHznHHKTE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=jjZFeY4OOTVhA4sboi2r+rEMylHdIoHMEp5tGiun34GMpih9aUJxxn44dKXHK2PlvY RdVmdY8OZDKWhUrLrexCwA8tl4YsSpVBMvSCxoywC8AAdHjXvr2wPhoAA05bKLIri0Gd Vsv2exat0yRj2WNLmPGmDrUyDUmbDFajiLw/c= Received: by 10.142.151.20 with SMTP id y20mr1321242wfd.220.1304023901526; Thu, 28 Apr 2011 13:51:41 -0700 (PDT) Received: from localhost.localdomain (are.twiddle.net [75.101.38.216]) by mx.google.com with ESMTPS id z10sm2266797wfj.12.2011.04.28.13.51.40 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Apr 2011 13:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Apr 2011 13:50:57 -0700 Message-Id: <1304023875-25040-16-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1304023875-25040-1-git-send-email-rth@twiddle.net> References: <1304023875-25040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.210.45 Subject: [Qemu-devel] [PATCH 15/33] target-alpha: Merge HW_REI and HW_RET implementations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/translate.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 9e1576d..09edb0f 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -2943,14 +2943,24 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) break; #endif case 0x1E: - /* HW_REI (PALcode) */ + /* HW_RET (PALcode) */ #if defined (CONFIG_USER_ONLY) goto invalid_opc; #else if (!ctx->pal_mode) goto invalid_opc; - gen_helper_hw_ret(cpu_ir[rb]); - break; + if (rb == 31) { + /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return + address from EXC_ADDR. This turns out to be useful for our + emulation PALcode, so continue to accept it. */ + TCGv tmp = tcg_temp_new(); + tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr)); + gen_helper_hw_ret(tmp); + tcg_temp_free(tmp); + } else { + gen_helper_hw_ret(cpu_ir[rb]); + } + return EXIT_PC_UPDATED; #endif case 0x1F: /* HW_ST (PALcode) */