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Thu, 21 Jun 2018 21:51:56 -0700 (PDT) Received: from rashmica.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v27-v6sm11874992pfi.23.2018.06.21.21.51.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jun 2018 21:51:56 -0700 (PDT) From: Rashmica Gupta To: pdbg@lists.ozlabs.org Date: Fri, 22 Jun 2018 14:51:13 +1000 Message-Id: <20180622045116.12059-6-rashmica.g@gmail.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180622045116.12059-1-rashmica.g@gmail.com> References: <20180622045116.12059-1-rashmica.g@gmail.com> Subject: [Pdbg] [PATCH 5/8] libpdbg: Add in mtocrf and putcr function X-BeenThere: pdbg@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: "mailing list for https://github.com/open-power/pdbg development" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: pdbg-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Pdbg" Signed-off-by: Rashmica Gupta --- libpdbg/chip.c | 36 ++++++++++++++++++++++++++++++++++++ libpdbg/libpdbg.h | 1 + libpdbg/operations.h | 1 + src/reg.c | 2 ++ 4 files changed, 40 insertions(+) diff --git a/libpdbg/chip.c b/libpdbg/chip.c index a4ee1e4..5e61fe2 100644 --- a/libpdbg/chip.c +++ b/libpdbg/chip.c @@ -52,6 +52,20 @@ static uint64_t mfocrf(uint64_t reg, uint64_t cr) return MFOCRF_OPCODE | (reg << 21) | (1U << (12 + cr)); } +static uint64_t mtocrf(uint64_t cr, uint64_t reg) +{ + if (reg > 31) { + PR_ERROR("Invalid register specified for mfocrf\n"); + exit(1); + } + if (cr > 7) { + PR_ERROR("Invalid CR field specified\n"); + exit(1); + } + + return MTOCRF_OPCODE | (reg << 21) | (1U << (12 + cr)); +} + static uint64_t mfnia(uint64_t reg) { if (reg > 31) @@ -347,6 +361,28 @@ int ram_getcr(struct pdbg_target *thread, uint32_t *value) return 0; } +int ram_putcr_field(struct pdbg_target *thread, int cr, uint32_t value) +{ + uint64_t opcodes[] = {mfspr(0, 277), mtocrf(cr, 0)}; + uint64_t results[] = {value, 0}; + + CHECK_ERR(ram_instructions(thread, opcodes, results, ARRAY_SIZE(opcodes), 0)); + return 0; +} + +int ram_putcr(struct pdbg_target *thread, uint32_t value) +{ + uint32_t cr_field; + int i; + + for (i = 0; i < 8; i++){ + cr_field = value & (0xf << 4*i); + ram_putcr_field(thread, i, cr_field); + } + + return 0; +} + int ram_putmsr(struct pdbg_target *thread, uint64_t value) { uint64_t opcodes[] = {mfspr(0, 277), mtmsr(0)}; diff --git a/libpdbg/libpdbg.h b/libpdbg/libpdbg.h index 28470c3..0b69554 100644 --- a/libpdbg/libpdbg.h +++ b/libpdbg/libpdbg.h @@ -139,6 +139,7 @@ int ram_putspr(struct pdbg_target *target, int spr, uint64_t val); int ram_putgpr(struct pdbg_target *target, int spr, uint64_t val); int ram_getmsr(struct pdbg_target *target, uint64_t *val); int ram_getcr(struct pdbg_target *thread, uint32_t *value); +int ram_putcr(struct pdbg_target *thread, uint32_t value); int ram_getnia(struct pdbg_target *target, uint64_t *val); int ram_getspr(struct pdbg_target *target, int spr, uint64_t *val); int ram_getgpr(struct pdbg_target *target, int gpr, uint64_t *val); diff --git a/libpdbg/operations.h b/libpdbg/operations.h index c7e3218..74baed8 100644 --- a/libpdbg/operations.h +++ b/libpdbg/operations.h @@ -73,6 +73,7 @@ #define MFXERF2_OPCODE 0x00000210UL #define MFXERF3_OPCODE 0x00000310UL #define MFOCRF_OPCODE 0x7c100026UL +#define MTOCRF_OPCODE 0x7C100120UL #define MFSPR_MASK (MFSPR_OPCODE | ((0x1f) << 16) | ((0x3e0) << 6)) #define MFXER_OPCODE (MFSPR_OPCODE | ((1 & 0x1f) << 16) | ((1 & 0x3e0) << 6)) #define MTXER_OPCODE (MTSPR_OPCODE | ((1 & 0x1f) << 16) | ((1 & 0x3e0) << 6)) diff --git a/src/reg.c b/src/reg.c index dbef0ef..65e8eb4 100644 --- a/src/reg.c +++ b/src/reg.c @@ -90,6 +90,8 @@ static int getprocreg(struct pdbg_target *target, uint32_t index, uint64_t *reg, rc = ram_getnia(target, &value); else if (*reg == REG_XER) rc = ram_getxer(target, (uint32_t *)&value); + else if (*reg == REG_CR) + rc = ram_getcr(target, (uint32_t *)&value); else if (*reg > REG_R31) rc = ram_getspr(target, *reg - REG_R31, &value); else if (*reg >= 0 && *reg <= 31)