diff mbox series

[05/11] hw/ssi/omap_spi: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Message ID 20180621180224.8312-6-f4bug@amsat.org
State New
Headers show
Series hw/arm: use qemu_log_mask instead of fprintf | expand

Commit Message

Philippe Mathieu-Daudé June 21, 2018, 6:02 p.m. UTC 
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/ssi/omap_spi.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

Comments

Alistair Francis June 21, 2018, 6:04 p.m. UTC | #1 
On Thu, Jun 21, 2018 at 11:02 AM, Philippe Mathieu-Daudé
<f4bug@amsat.org> wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/ssi/omap_spi.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
> index 34163e5646..f278a55160 100644
> --- a/hw/ssi/omap_spi.c
> +++ b/hw/ssi/omap_spi.c
> @@ -20,6 +20,7 @@
>   * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>   */
>  #include "qemu/osdep.h"
> +#include "qemu/log.h"
>  #include "hw/hw.h"
>  #include "hw/arm/omap.h"
>
> @@ -294,11 +295,15 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
>      case 0x2c: /* MCSPI_CHCONF */
>          if ((value ^ s->ch[ch].config) & (3 << 14))    /* DMAR | DMAW */
>              omap_mcspi_dmarequest_update(s->ch + ch);
> -        if (((value >> 12) & 3) == 3)                  /* TRM */
> -            fprintf(stderr, "%s: invalid TRM value (3)\n", __func__);
> -        if (((value >> 7) & 0x1f) < 3)                 /* WL */
> -            fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
> -                            __func__, (value >> 7) & 0x1f);
> +        if (((value >> 12) & 3) == 3) { /* TRM */
> +            qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
> +                          __func__);
> +        }
> +        if (((value >> 7) & 0x1f) < 3) { /* WL */
> +            qemu_log_mask(LOG_GUEST_ERROR,
> +                          "%s: invalid WL value (%" PRIx64 ")\n",
> +                          __func__, (value >> 7) & 0x1f);
> +        }
>          s->ch[ch].config = value & 0x7fffff;
>          break;
>
> --
> 2.18.0.rc2
>
>
diff mbox series

Patch

diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c
index 34163e5646..f278a55160 100644
--- a/hw/ssi/omap_spi.c
+++ b/hw/ssi/omap_spi.c
@@ -20,6 +20,7 @@ 
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "hw/hw.h"
 #include "hw/arm/omap.h"
 
@@ -294,11 +295,15 @@  static void omap_mcspi_write(void *opaque, hwaddr addr,
     case 0x2c:	/* MCSPI_CHCONF */
         if ((value ^ s->ch[ch].config) & (3 << 14))	/* DMAR | DMAW */
             omap_mcspi_dmarequest_update(s->ch + ch);
-        if (((value >> 12) & 3) == 3)			/* TRM */
-            fprintf(stderr, "%s: invalid TRM value (3)\n", __func__);
-        if (((value >> 7) & 0x1f) < 3)			/* WL */
-            fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
-                            __func__, (value >> 7) & 0x1f);
+        if (((value >> 12) & 3) == 3) { /* TRM */
+            qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
+                          __func__);
+        }
+        if (((value >> 7) & 0x1f) < 3) { /* WL */
+            qemu_log_mask(LOG_GUEST_ERROR,
+                          "%s: invalid WL value (%" PRIx64 ")\n",
+                          __func__, (value >> 7) & 0x1f);
+        }
         s->ch[ch].config = value & 0x7fffff;
         break;