From patchwork Mon Jun 18 20:52:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 931202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="hcqm6L7e"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 418jwk3yG6z9s2R for ; Tue, 19 Jun 2018 06:53:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936232AbeFRUxB (ORCPT ); Mon, 18 Jun 2018 16:53:01 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:40106 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935704AbeFRUw7 (ORCPT ); Mon, 18 Jun 2018 16:52:59 -0400 Received: by mail-pl0-f68.google.com with SMTP id t12-v6so9668512plo.7 for ; Mon, 18 Jun 2018 13:52:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=96USV6C54uRHxC6nrrC3LgcFLVwryPmux7y3++LNzZQ=; b=hcqm6L7eMzPEfJj0AmnEv7mAl5K0RywLLwodQdy3ef1AzGT5ufSLa+xjGXzPZlmnl5 L1CpRJSMrUl62zEv3Z+hninpfm+tv+6FW7gCFwRQECOdw4DTMIarqNj9t7KuyJDqT21n m9uHzXgmGYRllvBsoD7VH+pp5/zopelMwXeOk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=96USV6C54uRHxC6nrrC3LgcFLVwryPmux7y3++LNzZQ=; b=XcVo6N8fkNJ0KP6wqsHS/nPh4qRhkFwThJhRU+xoPHXE6Mj9KyTKno/hoICw22PpAQ kivdJHXe+fip8RWX7reYNaQAB7J/zfA8VAEnG6E8RPzdg7FGEu/37FNGe2DX2qD1LExb GX0r1B37FlBM+Hxq39HdQZ58yBdzg9MG3i2FmBNgxIl1Zq8TT451/sKODaw3uydKG6kO M8DL9z6viGRwjNAvSDfHbWEnpVMXdKesU7hkWZhR3TC3BlU38i8eaE7XaVtd7Kzz/WWa cekV2SbaPbftT0TtSyhyCAb4/MUS7jiBonAAm/e9S3m5AKfwH0f5bYxZYBVjUFCOioFh vCVQ== X-Gm-Message-State: APt69E2hvyUlFk4KcmoB5VuLSRjw872ODa61JO741QlSzIayfygAsX0R bBynohjKolezyiFwLZbCfJwpKw== X-Google-Smtp-Source: ADUXVKLoAE+Pv+Rkr4gEcmcvM5KCOABytlIVRcJkdojt6rMrNyX+m0erjzU0IqQ9D6YjBuYtofBniA== X-Received: by 2002:a17:902:64cf:: with SMTP id y15-v6mr15743339pli.53.1529355179005; Mon, 18 Jun 2018 13:52:59 -0700 (PDT) Received: from swboyd.mtv.corp.google.com ([2620:0:1000:1511:d30e:62c6:f82c:ff40]) by smtp.gmail.com with ESMTPSA id a27-v6sm27052196pfc.18.2018.06.18.13.52.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Jun 2018 13:52:58 -0700 (PDT) From: Stephen Boyd To: Linus Walleij Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Bjorn Andersson , Doug Anderson Subject: [PATCH 1/3] pinctrl: msm: Really mask level interrupts to prevent latching Date: Mon, 18 Jun 2018 13:52:53 -0700 Message-Id: <20180618205255.246104-2-swboyd@chromium.org> X-Mailer: git-send-email 2.18.0.rc1.244.gcf134e6275-goog In-Reply-To: <20180618205255.246104-1-swboyd@chromium.org> References: <20180618205255.246104-1-swboyd@chromium.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The interrupt controller hardware in this pin controller has two status enable bits. The first "normal" status enable bit enables or disables the summary interrupt line being raised when a gpio interrupt triggers and the "raw" status enable bit allows or prevents the hardware from latching an interrupt into the status register for a gpio interrupt. Currently we just toggle the "normal" status enable bit in the mask and unmask ops so that the summary irq interrupt going to the CPU's interrupt controller doesn't trigger for the masked gpio interrupt. For a level triggered interrupt, the flow would be as follows: the pin controller sees the interrupt, latches the status into the status register, raises the summary irq to the CPU, summary irq handler runs and calls handle_level_irq(), handle_level_irq() masks and acks the gpio interrupt, the interrupt handler runs, and finally unmask the interrupt. When the interrupt handler completes, we expect that the interrupt line level will go back to the deasserted state so the genirq code can unmask the interrupt without it triggering again. If we only mask the interrupt by clearing the "normal" status enable bit then we'll ack the interrupt but it will continue to show up as pending in the status register because the raw status bit is enabled, the hardware hasn't deasserted the line, and thus the asserted state latches into the status register again. When the hardware deasserts the interrupt the pin controller still thinks there is a pending unserviced level interrupt because it latched it earlier. This behavior causes software to see an extra interrupt for level type interrupts each time the interrupt is handled. Let's fix this by clearing the raw status enable bit for level type interrupts so that the hardware stops latching the status of the interrupt after we ack it. We don't do this for edge type interrupts because it seems that toggling the raw status enable bit for edge type interrupts causes spurious edge interrupts. Cc: Bjorn Andersson Cc: Doug Anderson Signed-off-by: Stephen Boyd --- drivers/pinctrl/qcom/pinctrl-msm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 0e22f52b2a19..3563c4394837 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -626,6 +626,19 @@ static void msm_gpio_irq_mask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); + /* + * Leaving the RAW_STATUS_EN bit enabled causes level interrupts that + * are still asserted to re-latch after we ack them. Clear the raw + * status enable bit too so the interrupt can't even latch into the + * hardware while it's masked, but only do this for level interrupts + * because edge interrupts have a problem with the raw status bit + * toggling and causing spurious interrupts. + */ + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) { + val &= ~BIT(g->intr_raw_status_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + } + val &= ~BIT(g->intr_enable_bit); writel(val, pctrl->regs + g->intr_cfg_reg); @@ -647,6 +660,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d) raw_spin_lock_irqsave(&pctrl->lock, flags); val = readl(pctrl->regs + g->intr_cfg_reg); + if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) { + val |= BIT(g->intr_raw_status_bit); + writel(val, pctrl->regs + g->intr_cfg_reg); + } val |= BIT(g->intr_enable_bit); writel(val, pctrl->regs + g->intr_cfg_reg);