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[U-Boot,3/4] ARM: rmobile: Fix CPGW address on V3M Eagle

Message ID 20180616020320.4221-3-marek.vasut+renesas@gmail.com
State Accepted
Commit c267952c41484dc1d8c73a7362bcabf33c8934e4
Delegated to: Marek Vasut
Headers show
Series [U-Boot,1/4] ARM: dts: rmobile: Add AVB pinmux on V3M Eagle | expand

Commit Message

Marek Vasut June 16, 2018, 2:03 a.m. UTC 
Fix the CPGWPR/CPGWPCR register address on V3M Eagle to unlock
access to the CPG clock control registers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
 board/renesas/eagle/eagle.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
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Patch

diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c
index 4bf0a202e0..7b89c10cc7 100644
--- a/board/renesas/eagle/eagle.c
+++ b/board/renesas/eagle/eagle.c
@@ -26,8 +26,8 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CPGWPR  0xE6150900
 #define CPGWPCR	0xE6150904
-#define CPGWPR  0xE615090C
 
 /* PLL */
 #define PLL0CR		0xE61500D8
@@ -54,8 +54,9 @@  void s_init(void)
 
 int board_early_init_f(void)
 {
-	writel(0xA5A5FFFF, CPGWPCR);
-	writel(0x5A5A0000, CPGWPR);
+	/* Unlock CPG access */
+	writel(0xA5A5FFFF, CPGWPR);
+	writel(0x5A5A0000, CPGWPCR);
 
 	/* TMU0 */
 	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);