| Message ID | c8c5ac270cd4e0e677219abcb83c8e402caf0146.1529085003.git.ivan.gorinov@intel.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | [U-Boot,v2] x86: Use microcode update from device tree for all processors | expand |
On Sat, Jun 16, 2018 at 2:01 AM, Ivan Gorinov <ivan.gorinov@intel.com> wrote: > Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies > the microcode update data block encoded in Device Tree to the bootstrap > processor but not passed to the other CPUs when multiprocessing is enabled. > > If the bootstrap processor successfully performs a microcode update > from Device Tree, use the same data block for the other processors. > > Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> > --- > arch/x86/cpu/i386/cpu.c | 3 ++- > arch/x86/cpu/intel_common/car.S | 2 ++ > arch/x86/cpu/intel_common/microcode.c | 10 +++++++--- > arch/x86/include/asm/microcode.h | 1 + > arch/x86/lib/fsp/fsp_car.S | 4 +++- > 5 files changed, 15 insertions(+), 5 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Mon, Jun 18, 2018 at 8:58 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Sat, Jun 16, 2018 at 2:01 AM, Ivan Gorinov <ivan.gorinov@intel.com> wrote: >> Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies >> the microcode update data block encoded in Device Tree to the bootstrap >> processor but not passed to the other CPUs when multiprocessing is enabled. >> >> If the bootstrap processor successfully performs a microcode update >> from Device Tree, use the same data block for the other processors. >> >> Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> >> --- >> arch/x86/cpu/i386/cpu.c | 3 ++- >> arch/x86/cpu/intel_common/car.S | 2 ++ >> arch/x86/cpu/intel_common/microcode.c | 10 +++++++--- >> arch/x86/include/asm/microcode.h | 1 + >> arch/x86/lib/fsp/fsp_car.S | 4 +++- >> 5 files changed, 15 insertions(+), 5 deletions(-) >> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> applied to u-boot-x86, thanks!
Hi Ivan, On Tue, Jun 19, 2018 at 9:19 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Mon, Jun 18, 2018 at 8:58 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >> On Sat, Jun 16, 2018 at 2:01 AM, Ivan Gorinov <ivan.gorinov@intel.com> wrote: >>> Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies >>> the microcode update data block encoded in Device Tree to the bootstrap >>> processor but not passed to the other CPUs when multiprocessing is enabled. >>> >>> If the bootstrap processor successfully performs a microcode update >>> from Device Tree, use the same data block for the other processors. >>> >>> Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> >>> --- >>> arch/x86/cpu/i386/cpu.c | 3 ++- >>> arch/x86/cpu/intel_common/car.S | 2 ++ >>> arch/x86/cpu/intel_common/microcode.c | 10 +++++++--- >>> arch/x86/include/asm/microcode.h | 1 + >>> arch/x86/lib/fsp/fsp_car.S | 4 +++- >>> 5 files changed, 15 insertions(+), 5 deletions(-) >>> >> >> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > > applied to u-boot-x86, thanks! This unfortunately breaks edison and qemu-x86. Can you please have a look? x86: + edison qemu-x86 +arch/x86/cpu/built-in.o: In function `x86_mp_init': +build/../arch/x86/cpu/i386/cpu.c:589: undefined reference to `ucode_base' Regards, Bin
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 208ef08..90e3e8b 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -22,6 +22,7 @@ #include <malloc.h> #include <asm/control_regs.h> #include <asm/cpu.h> +#include <asm/microcode.h> #include <asm/mp.h> #include <asm/msr.h> #include <asm/mtrr.h> @@ -585,7 +586,7 @@ int x86_mp_init(void) mp_params.parallel_microcode_load = 0, mp_params.flight_plan = &mp_steps[0]; mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = 0; + mp_params.microcode_pointer = (void *)ucode_base; if (mp_init(&mp_params)) { printf("Warning: MP init failure\n"); diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S index fe8dfbc..52a77bb 100644 --- a/arch/x86/cpu/intel_common/car.S +++ b/arch/x86/cpu/intel_common/car.S @@ -239,4 +239,6 @@ _dt_ucode_base_size: .globl ucode_base ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c index 11b1ec8..c7a539d 100644 --- a/arch/x86/cpu/intel_common/microcode.c +++ b/arch/x86/cpu/intel_common/microcode.c @@ -43,8 +43,6 @@ static int microcode_decode_node(const void *blob, int node, update->data = fdt_getprop(blob, node, "data", &update->size); if (!update->data) return -ENOENT; - update->data += UCODE_HEADER_LEN; - update->size -= UCODE_HEADER_LEN; update->header_version = fdtdec_get_int(blob, node, "intel,header-version", 0); @@ -124,6 +122,7 @@ static void microcode_read_cpu(struct microcode_update *cpu) int microcode_update_intel(void) { struct microcode_update cpu, update; + ulong address; const void *blob = gd->fdt_blob; int skipped; int count; @@ -167,7 +166,8 @@ int microcode_update_intel(void) skipped++; continue; } - wrmsr(MSR_IA32_UCODE_WRITE, (ulong)update.data, 0); + address = (ulong)update.data + UCODE_HEADER_LEN; + wrmsr(MSR_IA32_UCODE_WRITE, address, 0); rev = microcode_read_rev(); debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n", rev, update.date_code & 0xffff, @@ -178,5 +178,9 @@ int microcode_update_intel(void) return -EFAULT; } count++; + if (!ucode_base) { + ucode_base = (ulong)update.data; + ucode_size = update.size; + } } while (1); } diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index f7b32a5..4ab7504 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -10,6 +10,7 @@ /* This is a declaration for ucode_base in start.S */ extern u32 ucode_base; +extern u32 ucode_size; /** * microcode_update_intel() - Apply microcode updates diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S index 549d863..48edc83 100644 --- a/arch/x86/lib/fsp/fsp_car.S +++ b/arch/x86/lib/fsp/fsp_car.S @@ -102,8 +102,10 @@ temp_ram_init_params: _dt_ucode_base_size: /* These next two fields are filled in by ifdtool */ .globl ucode_base -ucode_base: /* Declared in micrcode.h */ +ucode_base: /* Declared in microcode.h */ .long 0 /* microcode base */ +.globl ucode_size +ucode_size: /* Declared in microcode.h */ .long 0 /* microcode size */ .long CONFIG_SYS_MONITOR_BASE /* code region base */ .long CONFIG_SYS_MONITOR_LEN /* code region size */
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies the microcode update data block encoded in Device Tree to the bootstrap processor but not passed to the other CPUs when multiprocessing is enabled. If the bootstrap processor successfully performs a microcode update from Device Tree, use the same data block for the other processors. Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com> --- arch/x86/cpu/i386/cpu.c | 3 ++- arch/x86/cpu/intel_common/car.S | 2 ++ arch/x86/cpu/intel_common/microcode.c | 10 +++++++--- arch/x86/include/asm/microcode.h | 1 + arch/x86/lib/fsp/fsp_car.S | 4 +++- 5 files changed, 15 insertions(+), 5 deletions(-)