[rs6000] Fix AIX expected builtin instruction counts

GCC Maintainers:

The following patch fixes the instruction count tests for various
builtin testcases that fail on AIX.  The expected instruction counts
differ in a few cases between Linux and AIX.  An AIX instruction target
was added to the instruction count tests that differ on AIX and Linux.
Additionally, the patch contains a fix for a count that is wrong in
general. 

The patch has been tested on 

    powerpc64le-unknown-linux-gnu (Power 8 LE)  
    powerpc64-unknown-linux-gnu (Power 8 BE)
    AIX 7200-00-01-1543 (Power 8 BE)

With no regressions.

Please let me know if the patch looks OK for GCC mainline. 

                         Carl Love
----------------------------------------------------------------------

gcc/testsuite/ChangeLog:

2018-06-12  Carl Love  <cel@us.ibm.com>

 	* gcc.target/powerpc/altivec-7.c: Add qualifiers for counts on AIX
	versus Linux.
	* gcc.target/powerpc/builtins-1.c: Add qualifiers for counts on AIX
	versus Linux.
	* gcc.target/powerpc/builtins-4.c: Add qualifiers for counts on AIX
	versus Linux.
 	* gcc.target/powerpc/vsx-vector-6.p7.c: Fix xxlnor BE expected count.
---
 gcc/testsuite/gcc.target/powerpc/altivec-7.c       | 17 +++++++++++------
 gcc/testsuite/gcc.target/powerpc/builtins-1.c      | 11 +++++++----
 gcc/testsuite/gcc.target/powerpc/builtins-4.c      |  7 ++++---
 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c |  2 +-
 4 files changed, 23 insertions(+), 14 deletions(-)

Hi!

On Thu, Jun 14, 2018 at 08:12:31AM -0700, Carl Love wrote:
> --- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
> @@ -85,17 +85,22 @@ int main ()
>  /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
>  /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
>  /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target le } } } */
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target { le && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target { be && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 0 { target { powerpc*-*-aix* } } } } */

AIX is always BE so you don't need the addition on the "le" line.

> --- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
> @@ -333,8 +333,9 @@ int main ()
>  /* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
>  /* { dg-final { scan-assembler-times "vmrglh" 8 } } */
>  /* { dg-final { scan-assembler-times "xxlnor" 6 } } */
> -/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
> -/* { dg-final { scan-assembler-times "xxlor" 7  { target { lp64 } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 7  { target { lp64 && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 7  { target { powerpc*-*-aix* } } } } */

I don't know what the correct count is for 64-bit AIX; I don't think it
is the same as with 32-bit AIX.

>  /* { dg-final { scan-assembler-times "vpksdus" 2 } } */
>  /* { dg-final { scan-assembler-times "vperm" 4 } } */
>  /* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
> @@ -343,8 +344,10 @@ int main ()
>  /* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
>  /* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
>  /* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
> -/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 && !powerpc*-*-\
> +aix* } } } */

I don't think continuation lines work for this.  It is fine to have longer
lines for dejagnu stuff.

> -/* { dg-final { scan-assembler-times "vsl"     45 { target le } } } */
> -/* { dg-final { scan-assembler-times "vsl"     45 { target { be && ilp32 } } } } */
> -/* { dg-final { scan-assembler-times "vsl"     59 { target { be && lp64  } } } } */
> +/* { dg-final { scan-assembler-times "vsl"     45 { target { le && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl"     45 { target { { be && ilp32 } && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl"     59 { target { { be && lp64  } && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl"     80 { target { powerpc*-*-aix* } } } } */

"vsl" will also pick up all "vslo", "vslv", "vsldoi" and whatnot.  Use \m
and \M ?

So the main problem here is these testcases are compiled with -O0 (and
they have to be, most of this is optimised away otherwise).  But at -O0
there is a whole bunch of register moves, which are xxlor for VSX registers.

Like a comment used to say:

/* We generate xxlor instructions for many reasons other than or'ing vector
   operands or calling __builtin_vec_or(), which  means we cannot rely on
   their usage counts being stable.  Therefore, we just ensure at least one
   xxlor instruction was generated.  */
/* { dg-final { scan-assembler "xxlor" } } */

and in another test we had:

/* { dg-final { scan-assembler-times {(?n)\mxxlor\M.*\mboolv4si3_internal\M} 6 } } */

(that needs -dp btw.)

Neither is pretty, but we cannot do better (or I don't see how); there is
no "xxmr" extended mnemonic for VSX register moves so we cannot see the
difference between register moves and IOR insns easily.


Segher

Segher:

Per our discussions, the previous patch had issues with the target
!powerpc*-*-aix* not working correctly and thus the instruction count
test was not being done.  I have addressed those issues and verified by
inspecting the gcc/testsuite/gcc/gcc.log file to make sure the test was
actually executed.

As for the issues with the xxlxor being used as a move instruction in
builtins-1.c, I moved vec_or instructions to a new file.  The number of
xxlor instructions from the vec_or test cases can now be cleanly
counted without the move instructions from other tests.

I found in a few places that by qualifying the instruction counts
better, I was able to remove the target for BE and LE and m32 versus
m64.

I added the -dp option to the vsx-vector-6.p7.c test file.

I have retested again on 

    powerpc64le-unknown-linux-gnu (Power 8 LE)  
    powerpc64-unknown-linux-gnu (Power 8 BE)
    AIX 7200-00-01-1543 (Power 8 BE)

With no regressions.

Please let me know if the patch looks OK for GCC mainline. 

                         Carl Love

----------------------------------------------------------------

gcc/testsuite/ChangeLog:

2018-06-18  Carl Love  <cel@us.ibm.com>

 	* gcc.target/powerpc/altivec-7.c: Add qualifiers for counts on AIX
	versus Linux.
	* gcc.target/powerpc/builtins-1.c: Move vec_or tests to a new file.
	Add powerpc*-*-aix* and powerpc*-*-linux* target qualifiers.
	* gcc.target/powerpc/builtins-4.c: Fix matching for vsl instructions.
	* gcc.target/powerpc/builtins-5.c: New test file for vec_or test cases.
 	* gcc.target/powerpc/vsx-vector-6.p7.c: Fix xxlnor BE expected count.
	Add -dp to dg-options, update expected counts.
---
 gcc/testsuite/gcc.target/powerpc/altivec-7.c       | 16 ++++----
 gcc/testsuite/gcc.target/powerpc/builtins-1.c      | 18 ++-------
 gcc/testsuite/gcc.target/powerpc/builtins-4.c      |  5 +--
 gcc/testsuite/gcc.target/powerpc/builtins-5.c      | 44 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c | 14 +++----
 5 files changed, 65 insertions(+), 32 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5.c

diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index b61092c..8d8559b 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -73,8 +73,8 @@ int main ()
      vec_unpackl                    vupkhsh
      vec_unpackl                    vupkhpx
      vec_unpackl                    vupkhsb
-     vec_andc                       xxnor
-                                    xxland
+     vec_andc                       xxlnor (vnor AIX)
+                                    xxland (vand AIX)
      vec_vxor                       xxlxor
      vec_vmsumubm                   vmsumubm
      vec_vmulesb                    vmulosb
@@ -85,17 +85,17 @@ int main ()
 /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
 /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
 /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target le } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target { powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 42 { target { powerpc*-*-aix* } } } } */
 /* { dg-final { scan-assembler-times "lvewx" 2 } } */
 /* { dg-final { scan-assembler-times "lvxl" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsh" 2 } } */
 /* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times {\mxxlnor\M|\mvnor\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxxland\M|\mvand\M} 4 } } */
+/* { dg-final { scan-assembler-times "xxlxor" 5 { target { powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times "xxlxor" 0 { target { powerpc*-*-aix* } } } } */
 /* { dg-final { scan-assembler-times "xxlandc" 0 } } */
-/* { dg-final { scan-assembler-times "lvx" 1 } } */
 /* { dg-final { scan-assembler-times "vmsumubm" 1 } } */
 /* { dg-final { scan-assembler-times "vupklpx" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsx" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 45727b9..0492bf6 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -81,14 +81,6 @@ int main ()
   vector unsigned long long uq = vec_nor (ua, ud);
   vector unsigned long long ur = vec_nor (ud, ua);
 
-  vector long long ls = vec_or (la, lb);
-  vector long long lt = vec_or (la, ld);
-  vector long long lu = vec_or (ld, la);
-
-  vector unsigned long long us = vec_or (ua, ub);
-  vector unsigned long long ut = vec_or (ua, ud);
-  vector unsigned long long uu = vec_or (ud, ua);
-
   vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
   vector unsigned char cbb = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
 
@@ -267,7 +259,6 @@ int main ()
   vector short signed int z_vss1 = vec_splat (ssa, 2);
   vector unsigned short int z_vuss1 = vec_splat (usa, 1);
 
-
   return 0;
 }
 
@@ -296,7 +287,6 @@ int main ()
    vec_mergeh          xxmrglw, vmrglh
    vec_mul             mulld | mullw, mulhwu
    vec_nor             xxlnor
-   vec_or              xxlor
    vec_packsu          vpksdus
    vec_                perm vperm
    vec_                round xvrdpi
@@ -333,8 +323,6 @@ int main ()
 /* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
 /* { dg-final { scan-assembler-times "vmrglh" 8 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 6 } } */
-/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
-/* { dg-final { scan-assembler-times "xxlor" 7  { target { lp64 } } } } */
 /* { dg-final { scan-assembler-times "vpksdus" 2 } } */
 /* { dg-final { scan-assembler-times "vperm" 4 } } */
 /* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
@@ -343,8 +331,10 @@ int main ()
 /* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
-/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target { ilp32 && powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target {ilp32 && powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times "bl .__divdi3" 2  { target { ilp32 && powerpc*-*-aix* } } } } */
+/* { dg-final { scan-assembler-times "bl .__udivdi3" 2  { target { ilp32 && powerpc*-*-aix* } } } } */
 /* { dg-final { scan-assembler-times "mullw" 12  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "mulhwu" 4  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "xxmrgld" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4.c b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
index c5249fe..66bfaf1 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
@@ -162,6 +162,5 @@ test_sll_vuill_vuill_vuc (vector unsigned long long int x,
 /* { dg-final { scan-assembler-times "xvnabsdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"      4 } } */
 /* { dg-final { scan-assembler-times "xxlor"     30 } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target le } } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times "vsl"     59 { target { be && lp64  } } } } */
+/* { dg-final { scan-assembler-times {\mvsl\M}   5 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5.c b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
new file mode 100644
index 0000000..38bad2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
@@ -0,0 +1,44 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
+
+#include <altivec.h>
+
+
+int main ()
+{
+  vector long long la = {5L, 14L};
+  vector long long lb = {3L, 86L};
+  vector bool long long ld = {0, -1};
+
+  vector unsigned long long ua = {5L, 14L};
+  vector unsigned long long ub = {3L, 86L};
+  vector bool long long ud = {0, -1};
+
+  /*  vec_or tests generate an xxlor instruction when compiled with -O0.  The xxlor
+      instructions get optimized away with higher optimization levels.
+      When compiling on Linux we see the xxlor instruction used as a move in various
+      places.  When compiling on AIX, a move instruction is used instead of the xxlor
+      instruction.  So, these tests have been isolated into a different file to limit
+      the xxlor instruction use to just the vex_or builtin tests.  */      
+      
+  vector long long ls = vec_or (la, lb);
+  vector long long lt = vec_or (la, ld);
+  vector long long lu = vec_or (ld, la);
+
+  vector unsigned long long us = vec_or (ua, ub);
+  vector unsigned long long ut = vec_or (ua, ud);
+  vector unsigned long long uu = vec_or (ud, ua);
+
+
+
+
+
+  return 0;
+}
+
+/* Expected results:
+   vec_or              xxlor    */
+
+/* { dg-final { scan-assembler-times "xxlor" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
index 66ec064..ab6e557 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2 -mcpu=power7" } */
+/* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
 
 
@@ -10,7 +10,7 @@
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
-/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */
@@ -30,21 +30,21 @@
 /* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmindp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 2 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 2 } } */
 /* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
 /* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 2 } } */
 /* { dg-final { scan-assembler-times "xxland" 13 } } */
 /* { dg-final { scan-assembler-times "xxlxor" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
 /* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
 /* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 7 } } */
 
 /* Source code for the test in vsx-vector-6.h */
 #include "vsx-vector-6.h"

Hi Carl,

On Mon, Jun 18, 2018 at 01:52:15PM -0700, Carl Love wrote:
> Per our discussions, the previous patch had issues with the target
> !powerpc*-*-aix* not working correctly and thus the instruction count
> test was not being done.  I have addressed those issues and verified by
> inspecting the gcc/testsuite/gcc/gcc.log file to make sure the test was
> actually executed.
> 
> As for the issues with the xxlxor being used as a move instruction in
> builtins-1.c, I moved vec_or instructions to a new file.  The number of
> xxlor instructions from the vec_or test cases can now be cleanly
> counted without the move instructions from other tests.

:-)

> I found in a few places that by qualifying the instruction counts
> better, I was able to remove the target for BE and LE and m32 versus
> m64.
> 
> I added the -dp option to the vsx-vector-6.p7.c test file.

But you do not use the -dp output it seems?  If you add it you can see the
difference between xxlor generated as an OR or just as a register me (by
looking at the pattern name); if you don't use that (like, you moved the
ORs to a separate file so you don't need it), don't use -dp.

> -     vec_andc                       xxnor
> -                                    xxland
> +     vec_andc                       xxlnor (vnor AIX)
> +                                    xxland (vand AIX)
>       vec_vxor                       xxlxor

Both vnor and xxlnor are correct everywhere; same for xxlxor and maybe
others.  Change the comments to just "vec_andc   xxlnor/vnor" etc.?

> +/* { dg-final { scan-assembler-times {\mxxlnor\M|\mvnor\M} 4 } } */
> +/* { dg-final { scan-assembler-times {\mxxland\M|\mvand\M} 4 } } */
> +/* { dg-final { scan-assembler-times "xxlxor" 5 { target { powerpc*-*-linux* } } } } */
> +/* { dg-final { scan-assembler-times "xxlxor" 0 { target { powerpc*-*-aix* } } } } */

Will this work with

> +/* { dg-final { scan-assembler-times {\mxxlxor\M|\mvxor\M} 4 } } */

?

> +/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target { ilp32 && powerpc*-*-linux* } } } } */
> +/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target {ilp32 && powerpc*-*-linux* } } } } */
> +/* { dg-final { scan-assembler-times "bl .__divdi3" 2  { target { ilp32 && powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "bl .__udivdi3" 2  { target { ilp32 && powerpc*-*-aix* } } } } */

What causes the difference here?  (Sorry if that is a dumb question, I didn't
look at the testcase).

Rest looks good, thanks!


Segher

Segher:

I believe I have addressed all of your concerns with the patch.

I have retested it and it looks good.

Please let me know if the patch looks OK for GCC mainline. 

                         Carl Love

----------------------------------------------------------------
From 8d354f93c5ddb5161b86e69abb64486657c6c92d Mon Sep 17 00:00:00 2001
From: Carl Love <carll@us.ibm.com>
Date: Wed, 20 Jun 2018 19:08:23 -0500
Subject: [PATCH] Fix expected instruction counts for tests

gcc/testsuite/ChangeLog:

2018-06-22  Carl Love  <cel@us.ibm.com>

 	* gcc.target/powerpc/altivec-7.c: Add qualifiers for counts on AIX
	versus Linux.  Change checks for xxlnor, xxland and xxlxor to also look
	for the vnor, vand and vxor instructions.
	* gcc.target/powerpc/builtins-1.c: Move vec_or tests to a new file.
	Remove counts for xxlor. Fix match on bl __divdi3 and bl __udivdi3.
	* gcc.target/powerpc/builtins-4.c: Fix matching for vsl instructions.
	* gcc.target/powerpc/builtins-5.c: New test file for vec_or test cases.
 	* gcc.target/powerpc/vsx-vector-6.p7.c: Fix xxlnor BE expected count.
	Add -dp to dg-options, update expected counts.
---
 gcc/testsuite/gcc.target/powerpc/altivec-7.c       | 15 ++++----
 gcc/testsuite/gcc.target/powerpc/builtins-1.c      | 16 ++-------
 gcc/testsuite/gcc.target/powerpc/builtins-4.c      |  5 ++-
 gcc/testsuite/gcc.target/powerpc/builtins-5.c      | 40 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c | 14 ++++----
 5 files changed, 58 insertions(+), 32 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-5.c

diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-7.c b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
index b61092c..ebc4a85 100644
--- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
@@ -73,8 +73,8 @@ int main ()
      vec_unpackl                    vupkhsh
      vec_unpackl                    vupkhpx
      vec_unpackl                    vupkhsb
-     vec_andc                       xxnor
-                                    xxland
+     vec_andc                       xxlnor (vnor AIX)
+                                    xxland (vand AIX)
      vec_vxor                       xxlxor
      vec_vmsumubm                   vmsumubm
      vec_vmulesb                    vmulosb
@@ -85,17 +85,16 @@ int main ()
 /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
 /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
 /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target le } } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 { target { powerpc*-*-linux* } } } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 42 { target { powerpc*-*-aix* } } } } */
 /* { dg-final { scan-assembler-times "lvewx" 2 } } */
 /* { dg-final { scan-assembler-times "lvxl" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsh" 2 } } */
 /* { dg-final { scan-assembler-times "vupkhsh" 2 } } */
-/* { dg-final { scan-assembler-times "xxlnor" 4 } } */
-/* { dg-final { scan-assembler-times "xxland" 4 } } */
-/* { dg-final { scan-assembler-times "xxlxor" 5 } } */
+/* { dg-final { scan-assembler-times {\mxxlnor\M|\mvnor\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxxland\M|\mvand\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mxxlxor\M|\mvxor\M} 5 } } */
 /* { dg-final { scan-assembler-times "xxlandc" 0 } } */
-/* { dg-final { scan-assembler-times "lvx" 1 } } */
 /* { dg-final { scan-assembler-times "vmsumubm" 1 } } */
 /* { dg-final { scan-assembler-times "vupklpx" 1 } } */
 /* { dg-final { scan-assembler-times "vupklsx" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 45727b9..3b4b27d 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -81,14 +81,6 @@ int main ()
   vector unsigned long long uq = vec_nor (ua, ud);
   vector unsigned long long ur = vec_nor (ud, ua);
 
-  vector long long ls = vec_or (la, lb);
-  vector long long lt = vec_or (la, ld);
-  vector long long lu = vec_or (ld, la);
-
-  vector unsigned long long us = vec_or (ua, ub);
-  vector unsigned long long ut = vec_or (ua, ud);
-  vector unsigned long long uu = vec_or (ud, ua);
-
   vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13};
   vector unsigned char cbb = {5,4,8,3,1,9,2,6,10,3,7,11,15,12,14,13};
 
@@ -267,7 +259,6 @@ int main ()
   vector short signed int z_vss1 = vec_splat (ssa, 2);
   vector unsigned short int z_vuss1 = vec_splat (usa, 1);
 
-
   return 0;
 }
 
@@ -296,7 +287,6 @@ int main ()
    vec_mergeh          xxmrglw, vmrglh
    vec_mul             mulld | mullw, mulhwu
    vec_nor             xxlnor
-   vec_or              xxlor
    vec_packsu          vpksdus
    vec_                perm vperm
    vec_                round xvrdpi
@@ -333,8 +323,6 @@ int main ()
 /* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
 /* { dg-final { scan-assembler-times "vmrglh" 8 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 6 } } */
-/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
-/* { dg-final { scan-assembler-times "xxlor" 7  { target { lp64 } } } } */
 /* { dg-final { scan-assembler-times "vpksdus" 2 } } */
 /* { dg-final { scan-assembler-times "vperm" 4 } } */
 /* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
@@ -343,8 +331,8 @@ int main ()
 /* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
 /* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
-/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2  { target { ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2  { target {ilp32 } } } } */
 /* { dg-final { scan-assembler-times "mullw" 12  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "mulhwu" 4  { target ilp32 } } } */
 /* { dg-final { scan-assembler-times "xxmrgld" 0 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4.c b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
index c5249fe..66bfaf1 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-4.c
@@ -162,6 +162,5 @@ test_sll_vuill_vuill_vuc (vector unsigned long long int x,
 /* { dg-final { scan-assembler-times "xvnabsdp"  1 } } */
 /* { dg-final { scan-assembler-times "vslo"      4 } } */
 /* { dg-final { scan-assembler-times "xxlor"     30 } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target le } } } */
-/* { dg-final { scan-assembler-times "vsl"     45 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times "vsl"     59 { target { be && lp64  } } } } */
+/* { dg-final { scan-assembler-times {\mvsl\M}   5 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-5.c b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
new file mode 100644
index 0000000..a4bb8fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-5.c
@@ -0,0 +1,40 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O0 -mno-fold-gimple -dp" } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
+
+#include <altivec.h>
+
+
+int main ()
+{
+  vector long long la = {5L, 14L};
+  vector long long lb = {3L, 86L};
+  vector bool long long ld = {0, -1};
+
+  vector unsigned long long ua = {5L, 14L};
+  vector unsigned long long ub = {3L, 86L};
+  vector bool long long ud = {0, -1};
+
+  /*  vec_or tests generate an xxlor instruction when compiled with -O0.  The xxlor
+      instructions get optimized away with higher optimization levels.
+      When compiling on Linux we see the xxlor instruction used as a move in various
+      places.  When compiling on AIX, a move instruction is used instead of the xxlor
+      instruction.  So, these tests have been isolated into a different file to limit
+      the xxlor instruction use to just the vex_or builtin tests.  */      
+      
+  vector long long ls = vec_or (la, lb);
+  vector long long lt = vec_or (la, ld);
+  vector long long lu = vec_or (ld, la);
+
+  vector unsigned long long us = vec_or (ua, ub);
+  vector unsigned long long ut = vec_or (ua, ud);
+  vector unsigned long long uu = vec_or (ud, ua);
+
+  return 0;
+}
+
+/* Expected results:
+   vec_or              xxlor    */
+
+/* { dg-final { scan-assembler-times "xxlor" 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
index 66ec064..ab6e557 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
 /* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
-/* { dg-options "-mvsx -O2 -mcpu=power7" } */
+/* { dg-options "-mvsx -O2 -mcpu=power7 -dp" } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
 
 
@@ -10,7 +10,7 @@
 /* { dg-final { scan-assembler-times "xvabsdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvadddp" 1 } } */
 /* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */
-/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */
+/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */
 /* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */
@@ -30,21 +30,21 @@
 /* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmindp" 1 } } */
 /* { dg-final { scan-assembler-times "xvmuldp" 1 } } */
-/* { dg-final { scan-assembler-times "vperm" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */
+/* { dg-final { scan-assembler-times "vperm" 2 } } */
+/* { dg-final { scan-assembler-times "xvrdpic" 2 } } */
 /* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */
 /* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */
 /* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */
 /* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */
-/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */
+/* { dg-final { scan-assembler-times "vmsumshs" 2 } } */
 /* { dg-final { scan-assembler-times "xxland" 13 } } */
 /* { dg-final { scan-assembler-times "xxlxor" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 2 } } */
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
 /* { dg-final { scan-assembler-times "xvrdpip" 1 } } */
 /* { dg-final { scan-assembler-times "xvdivdp" 1 } } */
-/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */
+/* { dg-final { scan-assembler-times "xvrdpi" 7 } } */
 
 /* Source code for the test in vsx-vector-6.h */
 #include "vsx-vector-6.h"

Hi Carl,

On Wed, Jun 20, 2018 at 05:09:00PM -0700, Carl Love wrote:
> I believe I have addressed all of your concerns with the patch.
> 
> I have retested it and it looks good.

It looks good indeed.  Please commit, thanks!

I noticed one more thing (follow-up patch?)

>  /* { dg-final { scan-assembler-times "divd" 8  { target lp64 } } } */
>  /* { dg-final { scan-assembler-times "divdu" 2  { target lp64 } } } */
>  /* { dg-final { scan-assembler-times "mulld" 4  { target lp64 } } } */
> -/* { dg-final { scan-assembler-times "bl __divdi3" 3  { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times "bl __udivdi3" 3  { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\mbl __divdi3\M} 2  { target { ilp32 } } } } */
> +/* { dg-final { scan-assembler-times {\mbl __udivdi3\M} 2  { target {ilp32 } } } } */

The test for "divd" will count those __divdi3, __udivdi3 as well.  It also
counts divdu.

Putting \m\M around most mnemonics helps.

Cheers,


Segher