| Message ID | 4a37904491c4ef26ad7aacac9d48618b3a8cf3e3.1528968775.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | e90d2659e46ab9483c24e08611c06922a8ec25d4 |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | serial: zynq: Fix serial driver | expand |
On 14 June 2018 at 03:32, Michal Simek <michal.simek@xilinx.com> wrote: > Change logic and put char to fifo till there is a space in output fifo. > Origin logic was that output fifo needs to be empty. It means only one > char was in output queue. > Also remove unused ZYNQ_UART_SR_TXEMPTY macro. > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/serial/serial_zynq.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 7a6f822c26ac..4ae24939ab23 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -15,8 +15,8 @@ #include <linux/compiler.h> #include <serial.h> -#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */ #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ +#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ @@ -93,7 +93,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) return -EAGAIN; writel(c, ®s->tx_rx_fifo);
Change logic and put char to fifo till there is a space in output fifo. Origin logic was that output fifo needs to be empty. It means only one char was in output queue. Also remove unused ZYNQ_UART_SR_TXEMPTY macro. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- drivers/serial/serial_zynq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)