From patchwork Wed Jun 13 19:36:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 929058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-i2c-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 415cSv4ky2z9s4w for ; Thu, 14 Jun 2018 05:36:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935704AbeFMTgm (ORCPT ); Wed, 13 Jun 2018 15:36:42 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:52420 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S935619AbeFMTgh (ORCPT ); Wed, 13 Jun 2018 15:36:37 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w5DJYImv041635 for ; Wed, 13 Jun 2018 15:36:36 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2jk5k8kbeu-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 13 Jun 2018 15:36:36 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 13 Jun 2018 13:36:35 -0600 Received: from b03cxnp07029.gho.boulder.ibm.com (9.17.130.16) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 13 Jun 2018 13:36:30 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w5DJaTIK9634258 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Jun 2018 12:36:29 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C2271C6059; Wed, 13 Jun 2018 13:36:29 -0600 (MDT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 282A2C6057; Wed, 13 Jun 2018 13:36:29 -0600 (MDT) Received: from talon7.ibm.com (unknown [9.41.102.69]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 13 Jun 2018 13:36:29 -0600 (MDT) From: Eddie James To: linux-i2c@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, wsa@the-dreams.de, robh+dt@kernel.org, benh@kernel.crashing.org, joel@jms.id.au, mark.rutland@arm.com, gregkh@linuxfoundation.org, rdunlap@infradead.org, andy.shevchenko@gmail.com, peda@axentia.se, Eddie James Subject: [PATCH v10 4/7] i2c: fsi: Add abort and hardware reset procedures Date: Wed, 13 Jun 2018 14:36:16 -0500 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1528918579-27602-1-git-send-email-eajames@linux.vnet.ibm.com> References: <1528918579-27602-1-git-send-email-eajames@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18061319-0004-0000-0000-00001452EB7B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009184; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000265; SDB=6.01046493; UDB=6.00535962; IPR=6.00825469; MB=3.00021628; MTD=3.00000008; XFM=3.00000015; UTC=2018-06-13 19:36:34 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18061319-0005-0000-0000-000087BADDA9 Message-Id: <1528918579-27602-5-git-send-email-eajames@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-06-13_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1805220000 definitions=main-1806130207 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add abort procedure for failed transfers. Add engine and bus reset procedures to recover from as many faults as possible. Signed-off-by: Eddie James --- drivers/i2c/busses/i2c-fsi.c | 179 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/drivers/i2c/busses/i2c-fsi.c b/drivers/i2c/busses/i2c-fsi.c index 695818f..4611a0b 100644 --- a/drivers/i2c/busses/i2c-fsi.c +++ b/drivers/i2c/busses/i2c-fsi.c @@ -12,10 +12,12 @@ #include #include +#include #include #include #include #include +#include #include #include #include @@ -128,6 +130,20 @@ #define I2C_ESTAT_SELF_BUSY BIT(6) #define I2C_ESTAT_VERSION GENMASK(4, 0) +/* port busy register */ +#define I2C_PORT_BUSY_RESET BIT(31) + +/* wait for command complete or data request */ +#define I2C_CMD_SLEEP_MAX_US 500 +#define I2C_CMD_SLEEP_MIN_US 50 + +/* wait after reset; choose time from legacy driver */ +#define I2C_RESET_SLEEP_MAX_US 2000 +#define I2C_RESET_SLEEP_MIN_US 1000 + +/* choose timeout length from legacy driver; it's well tested */ +#define I2C_ABORT_TIMEOUT msecs_to_jiffies(100) + struct fsi_i2c_master { struct fsi_device *fsi; u8 fifo_size; @@ -214,6 +230,169 @@ static int fsi_i2c_set_port(struct fsi_i2c_port *port) return fsi_i2c_write_reg(fsi, I2C_FSI_RESET_ERR, &dummy); } +static int fsi_i2c_reset_bus(struct fsi_i2c_master *i2c) +{ + int i, rc; + u32 mode, stat, ext, dummy = 0; + + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode); + if (rc) + return rc; + + mode |= I2C_MODE_DIAG; + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); + if (rc) + return rc; + + for (i = 0; i < 9; i++) { + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SCL, &dummy); + if (rc) + return rc; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SCL, &dummy); + if (rc) + return rc; + } + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SCL, &dummy); + if (rc) + return rc; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SDA, &dummy); + if (rc) + return rc; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SCL, &dummy); + if (rc) + return rc; + + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SDA, &dummy); + if (rc) + return rc; + + mode &= ~I2C_MODE_DIAG; + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); + if (rc) + return rc; + + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat); + if (rc) + return rc; + + /* check for hardware fault */ + if (!(stat & I2C_STAT_SCL_IN) || !(stat & I2C_STAT_SDA_IN)) { + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &ext); + if (rc) + return rc; + + dev_err(&i2c->fsi->dev, "bus stuck status[%08X] ext[%08X]\n", + stat, ext); + } + + return 0; +} + +static int fsi_i2c_reset(struct fsi_i2c_master *i2c, u16 port) +{ + int rc; + u32 mode, stat, dummy = 0; + + /* reset engine */ + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy); + if (rc) + return rc; + + /* re-init engine */ + rc = fsi_i2c_dev_init(i2c); + if (rc) + return rc; + + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode); + if (rc) + return rc; + + /* set port; default after reset is 0 */ + if (port) { + mode &= ~I2C_MODE_PORT; + mode |= FIELD_PREP(I2C_MODE_PORT, port); + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode); + if (rc) + return rc; + } + + /* reset busy register; hw workaround */ + dummy = I2C_PORT_BUSY_RESET; + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_PORT_BUSY, &dummy); + if (rc) + return rc; + + /* force bus reset */ + rc = fsi_i2c_reset_bus(i2c); + if (rc) + return rc; + + /* reset errors */ + dummy = 0; + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_ERR, &dummy); + if (rc) + return rc; + + /* wait for command complete */ + usleep_range(I2C_RESET_SLEEP_MIN_US, I2C_RESET_SLEEP_MAX_US); + + rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat); + if (rc) + return rc; + + if (stat & I2C_STAT_CMD_COMP) + return rc; + + /* failed to get command complete; reset engine again */ + rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy); + if (rc) + return rc; + + /* re-init engine again */ + return fsi_i2c_dev_init(i2c); +} + +static int fsi_i2c_abort(struct fsi_i2c_port *port, u32 status) +{ + int rc; + unsigned long start; + u32 cmd = I2C_CMD_WITH_STOP; + struct fsi_device *fsi = port->master->fsi; + + rc = fsi_i2c_reset(port->master, port->port); + if (rc) + return rc; + + /* skip final stop command for these errors */ + if (status & (I2C_STAT_PARITY | I2C_STAT_LOST_ARB | I2C_STAT_STOP_ERR)) + return 0; + + /* write stop command */ + rc = fsi_i2c_write_reg(fsi, I2C_FSI_CMD, &cmd); + if (rc) + return rc; + + /* wait until we see command complete in the master */ + start = jiffies; + + do { + rc = fsi_i2c_read_reg(fsi, I2C_FSI_STAT, &status); + if (rc) + return rc; + + if (status & I2C_STAT_CMD_COMP) + return 0; + + usleep_range(I2C_CMD_SLEEP_MIN_US, I2C_CMD_SLEEP_MAX_US); + } while (time_after(start + I2C_ABORT_TIMEOUT, jiffies)); + + return -ETIMEDOUT; +} + static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) {