diff mbox series

[U-Boot] common: Fix cpu nr type which is always unsigned type

Message ID 17a79c409220543ddae1d6947e60b9f036cbf836.1528872988.git.michal.simek@xilinx.com
State Accepted
Commit 20b016a33665f7b3ff875b4b7063180eb955f092
Delegated to: Tom Rini
Headers show
Series [U-Boot] common: Fix cpu nr type which is always unsigned type | expand

Commit Message

Michal Simek June 13, 2018, 6:56 a.m. UTC 
cpu_cmd() is reading cpu number via simple_strtoul() which is always
unsigned type.
Platform code implementations are not expecting that nr can be negative
and there is not checking in the code for that too.

This patch is using u32 type for cpu number to make sure that platform
code get proper value range.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/cpu/armv8/fsl-layerscape/mp.c |  8 ++++----
 arch/arm/cpu/armv8/zynqmp/mp.c         |  8 ++++----
 arch/arm/mach-imx/mx6/mp.c             |  8 ++++----
 arch/powerpc/cpu/mpc85xx/mp.c          | 10 +++++-----
 arch/powerpc/cpu/mpc86xx/mp.c          |  8 ++++----
 include/common.h                       |  8 ++++----
 6 files changed, 25 insertions(+), 25 deletions(-)

Comments

Tom Rini June 19, 2018, 6:43 p.m. UTC | #1 
On Wed, Jun 13, 2018 at 08:56:31AM +0200, Michal Simek wrote:

> cpu_cmd() is reading cpu number via simple_strtoul() which is always
> unsigned type.
> Platform code implementations are not expecting that nr can be negative
> and there is not checking in the code for that too.
> 
> This patch is using u32 type for cpu number to make sure that platform
> code get proper value range.
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index dd89d0a83f89..7627fd13e7d8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -191,14 +191,14 @@  int is_core_online(u64 cpu_id)
 	return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
 }
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	puts("Feature is not implemented.\n");
 
 	return 0;
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	puts("Feature is not implemented.\n");
 
@@ -231,7 +231,7 @@  static int core_to_pos(int nr)
 	return i;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	u64 *table;
 	int pos;
@@ -257,7 +257,7 @@  int cpu_status(int nr)
 	return 0;
 }
 
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
 {
 	u64 boot_addr;
 	u64 *table = (u64 *)get_spin_tbl_addr();
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
index 7e270a7dc232..2a71870ae7bc 100644
--- a/arch/arm/cpu/armv8/zynqmp/mp.c
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -45,7 +45,7 @@  int is_core_valid(unsigned int core)
 	return 0;
 }
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	puts("Feature is not implemented.\n");
 	return 0;
@@ -131,7 +131,7 @@  static void enable_clock_r5(void)
 	udelay(0x500);
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 		u32 val = readl(&crfapb_base->rst_fpd_apu);
@@ -144,7 +144,7 @@  int cpu_disable(int nr)
 	return 0;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 		u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
@@ -220,7 +220,7 @@  void initialize_tcm(bool mode)
 	}
 }
 
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
 {
 	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
 		u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
diff --git a/arch/arm/mach-imx/mx6/mp.c b/arch/arm/mach-imx/mx6/mp.c
index c3806dca3ad0..eda168d86711 100644
--- a/arch/arm/mach-imx/mx6/mp.c
+++ b/arch/arm/mach-imx/mx6/mp.c
@@ -29,20 +29,20 @@  static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
 	SRC_SCR_CORE_3_ENABLE_MASK
 };
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	/* Software reset of the CPU N */
 	src->scr |= cpu_reset_mask[nr];
 	return 0;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
 	return 0;
 }
 
-int cpu_release(int nr, int argc, char *const argv[])
+int cpu_release(u32 nr, int argc, char *const argv[])
 {
 	uint32_t boot_addr;
 
@@ -78,7 +78,7 @@  int is_core_valid(unsigned int core)
 	return 1;
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	/* Disable the CPU N */
 	src->scr &= ~cpu_ctrl_mask[nr];
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 42501ca3cec5..b0aa72ed6e02 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -42,7 +42,7 @@  int hold_cores_in_reset(int verbose)
 	return 0;
 }
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	out_be32(&pic->pir, 1 << nr);
@@ -53,7 +53,7 @@  int cpu_reset(int nr)
 	return 0;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	u32 *table, id = get_my_id();
 
@@ -79,7 +79,7 @@  int cpu_status(int nr)
 }
 
 #ifdef CONFIG_FSL_CORENET
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
@@ -95,7 +95,7 @@  int is_core_disabled(int nr) {
 	return (coredisrl & (1 << nr));
 }
 #else
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
@@ -137,7 +137,7 @@  static u8 boot_entry_map[4] = {
 	BOOT_ENTRY_R3_LOWER,
 };
 
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
 {
 	u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 	u64 boot_addr;
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
index 97bd160df8a5..ce300eac5b0e 100644
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ b/arch/powerpc/cpu/mpc86xx/mp.c
@@ -13,7 +13,7 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int cpu_reset(int nr)
+int cpu_reset(u32 nr)
 {
 	/* dummy function so common/cmd_mp.c will build
 	 * should be implemented in the future, when cpu_release()
@@ -23,13 +23,13 @@  int cpu_reset(int nr)
 	return 1;
 }
 
-int cpu_status(int nr)
+int cpu_status(u32 nr)
 {
 	/* dummy function so common/cmd_mp.c will build */
 	return 0;
 }
 
-int cpu_disable(int nr)
+int cpu_disable(u32 nr)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
@@ -66,7 +66,7 @@  int is_core_disabled(int nr) {
 	return 0;
 }
 
-int cpu_release(int nr, int argc, char * const argv[])
+int cpu_release(u32 nr, int argc, char * const argv[])
 {
 	/* dummy function so common/cmd_mp.c will build
 	 * should be implemented in the future */
diff --git a/include/common.h b/include/common.h
index 60c79137e212..940161f1758b 100644
--- a/include/common.h
+++ b/include/common.h
@@ -536,10 +536,10 @@  void show_activity(int arg);
 
 /* Multicore arch functions */
 #ifdef CONFIG_MP
-int cpu_status(int nr);
-int cpu_reset(int nr);
-int cpu_disable(int nr);
-int cpu_release(int nr, int argc, char * const argv[]);
+int cpu_status(u32 nr);
+int cpu_reset(u32 nr);
+int cpu_disable(u32 nr);
+int cpu_release(u32 nr, int argc, char * const argv[]);
 #endif
 
 #else	/* __ASSEMBLY__ */