From patchwork Tue Jun 12 20:00:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 928472 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=siol.net Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41514r1JbDz9s0w for ; Wed, 13 Jun 2018 06:02:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934244AbeFLUCR (ORCPT ); Tue, 12 Jun 2018 16:02:17 -0400 Received: from mailoutvs55.siol.net ([185.57.226.246]:38448 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933611AbeFLUCP (ORCPT ); Tue, 12 Jun 2018 16:02:15 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id C41345221F0; Tue, 12 Jun 2018 22:02:13 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta12.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id lSC-0eqVauJZ; Tue, 12 Jun 2018 22:02:13 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id 47408521DC5; Tue, 12 Jun 2018 22:02:13 +0200 (CEST) Received: from localhost.localdomain (unknown [194.152.15.144]) (Authenticated sender: 031275009) by mail.siol.net (Zimbra) with ESMTPSA id C1C0E5221F0; Tue, 12 Jun 2018 22:02:10 +0200 (CEST) From: Jernej Skrabec To: maxime.ripard@bootlin.com, wens@csie.org, robh+dt@kernel.org Cc: airlied@linux.ie, gustavo@padovan.org, maarten.lankhorst@linux.intel.com, seanpaul@chromium.org, mark.rutland@arm.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 10/27] dt-bindings: display: sun4i-drm: Add R40 TV TCON description Date: Tue, 12 Jun 2018 22:00:19 +0200 Message-Id: <20180612200036.21483-11-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net> References: <20180612200036.21483-1-jernej.skrabec@siol.net> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TCON description is expanded with R40 TV TCON compatibles. TV TCONs, which are connected to TCON TOP muxes, such as those on R40 SoC, also needs additional clock gate to be specified. Signed-off-by: Jernej Skrabec Acked-by: Rob Herring --- .../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index ef64c589a4b3..68c4b2995624 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -145,6 +145,7 @@ Required properties: * allwinner,sun8i-a33-tcon * allwinner,sun8i-a83t-tcon-lcd * allwinner,sun8i-a83t-tcon-tv + * allwinner,sun8i-r40-tcon-tv * allwinner,sun8i-v3s-tcon * allwinner,sun9i-a80-tcon-lcd * allwinner,sun9i-a80-tcon-tv @@ -178,8 +179,10 @@ For TCONs with channel 0, there is one more clock required: - 'tcon-ch0': The clock driving the TCON channel 0 For TCONs with channel 1, there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 +TV TCONs which are connected to TCON TOP (found in R40 SoC) need one more clock: + - 'tcon-top': TV TCON gate found in TCON TOP unit -When TCON support LVDS (all TCONs except TV TCON on A83T and those found +When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found in A13, H3, H5 and V3s SoCs), you need one more reset line: - 'lvds': The reset line driving the LVDS logic