plat/qemu: add PNOR support

Message ID 20180611154822.3168-1-clg@kaod.org
State Superseded
Headers show
Series
  • plat/qemu: add PNOR support
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Commit Message

Cédric Le Goater June 11, 2018, 3:48 p.m.
To access the PNOR, OPAL/skiboot drives the BMC SPI controller using
the iLPC2AHB device of the BMC SuperIO controller and accesses the
flash contents using the LPC FW address space on which the PNOR is
remapped.

The QEMU PowerNV machine now integrates such models (SuperIO
controller, iLPC2AHB device) and also a pseudo Aspeed SoC AHB memory
space populated with the SPI controller registers (same model as for
ARM). The AHB window giving access to the contents of the BMC SPI
controller flash modules is mapped on the LPC FW address space.

The change should be compatible for machine without PNOR support.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 The resulting machine is quite hybrid as it is mixing ARM and PPC
 models but it is a good way to validate their exactitude and
 completeness. We still need to work on model for the LPC bus.

platforms/qemu/qemu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Patch

diff --git a/platforms/qemu/qemu.c b/platforms/qemu/qemu.c
index 85ca213c29af..a564644291f9 100644
--- a/platforms/qemu/qemu.c
+++ b/platforms/qemu/qemu.c
@@ -24,6 +24,8 @@ 
 #include <bt.h>
 #include <errorlog.h>
 #include <ipmi.h>
+#include <ast.h>
+#include <platforms/astbmc/astbmc.h>
 
 /* BT config */
 #define BT_IO_BASE	0xe4
@@ -78,6 +80,9 @@  static void qemu_ipmi_setenables(void)
 
 static void qemu_init(void)
 {
+	/* Initialize PNOR/NVRAM */
+	pnor_init();
+
 	/* Setup UART console for use by Linux via OPAL API */
 	set_opal_console(&uart_opal_con);
 
@@ -241,6 +246,9 @@  static bool qemu_probe(void)
 
 	psi_set_external_irq_policy(EXTERNAL_IRQ_POLICY_SKIBOOT);
 
+	/* Initialize AHB accesses via AST2400 */
+	ast_io_init();
+
 	/* Setup UART and use it as console */
 	uart_init();