From patchwork Mon Jun 11 08:20:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 927525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dr3NswZn"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4145Yk1m7yz9rxs for ; Mon, 11 Jun 2018 18:20:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754066AbeFKIUl (ORCPT ); Mon, 11 Jun 2018 04:20:41 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:41944 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754010AbeFKIUk (ORCPT ); Mon, 11 Jun 2018 04:20:40 -0400 Received: by mail-wr0-f194.google.com with SMTP id h10-v6so19343568wrq.8; Mon, 11 Jun 2018 01:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=4o1MOGC/WOU4N+uFxuXtZKRPPBhVWBD8k1cL92YnLeo=; b=dr3NswZniUUJqkyn4Sf1zEwzlFgf6E7WqQmP3VOHbhrlovKi9OSI88ZxqyDMnjI00P 5jt5iYCBrVkhGW0FDPjxpezbAohqlc3u8GexSl9sKYtnFAh/ghJmpfLIpk9Ghu/a0yko RWPjncyLzIa589zlH0nqSERnEYcuedBiyQaThTx/SOo8jStCmSF9D7Q4RmzX6yarbOIU OpKdz7cQfOMpjwhLX9Pwnh3IlUPsbhlfxCvw19WAs3NpvTzEml1laLLqaiRqY/GeHbco Vn3kdIHL3yU+LuUoob3SIu8Qp1J+7k/SLCMjvMTqHJYByyUmDO4tWZJnRzGkqByn3rxI XgiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=4o1MOGC/WOU4N+uFxuXtZKRPPBhVWBD8k1cL92YnLeo=; b=PSK+iYimMx7boH9HCaUT5HPbDhOPHZu2R+78uegB8LVXhPPIgKGqPGVtAgDVx6OArB phizdIXQn+U+ukywT8pwibXmvApleUYsZZupPTZBc9JovrEKfYDd97JyH4ZWw31QRKNI S6lhHHkSpSLI0Dt19UM27H3Ix+wHklnhNJfmT2VYcpiOOwZfJz8aiJNECsPo9hQZUStx TScZ5QEj8AWFGzYXP1ER6ItBjcqEqzSPIc+H4Dffio0Uu3uqXjzu+It3XyxTx+GrPhz2 kvi+RBQjfFdrlFZDKpZZ1AW/nai/yWXZM2zD8RE/bKeY1bFJ3Hedcz+1NDFG0UCpx5N0 12dQ== X-Gm-Message-State: APt69E2rttzlQbKss/8ovGb3C2IK/Ug6dRjko/sa2vX4xZadfAdwLUfM 7G9u8oC7eFf+yKhZEdmthow= X-Google-Smtp-Source: ADUXVKLU/wLrSAEjB18CkIVKUWM4psIsLSCjL87AVkdOI+iPQlS+4q+RQFIVtx1Me5XlDfBW3T+UuA== X-Received: by 2002:adf:ac69:: with SMTP id v96-v6mr11664386wrc.5.1528705239075; Mon, 11 Jun 2018 01:20:39 -0700 (PDT) Received: from localhost (pD9E510DD.dip0.t-ipconnect.de. [217.229.16.221]) by smtp.gmail.com with ESMTPSA id t17-v6sm19614544wrr.82.2018.06.11.01.20.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Jun 2018 01:20:38 -0700 (PDT) From: Thierry Reding To: Michael Turquette , Stephen Boyd Cc: Peter De Schrijver , Dmitry Osipenko , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] clk: tegra: Make vde a child of pll_c3 Date: Mon, 11 Jun 2018 10:20:37 +0200 Message-Id: <20180611082037.31796-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra124.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index f5048f82c0b9..b6cf28ca2ed2 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1267,7 +1267,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, { TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 }, - { TEGRA124_CLK_VDE, TEGRA124_CLK_CLK_MAX, 600000000, 0 }, + { TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 }, { TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 }, { TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 }, { TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },