From patchwork Mon Jun 11 08:18:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 927524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="UHxqNvgw"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4145Wl0FBCz9rxs for ; Mon, 11 Jun 2018 18:18:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754066AbeFKIS5 (ORCPT ); Mon, 11 Jun 2018 04:18:57 -0400 Received: from mail-wr0-f194.google.com ([209.85.128.194]:45512 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754044AbeFKIS5 (ORCPT ); Mon, 11 Jun 2018 04:18:57 -0400 Received: by mail-wr0-f194.google.com with SMTP id o12-v6so19332119wrm.12; Mon, 11 Jun 2018 01:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=zeRsPUGVPv9WLg9yQUCp/wsgSGRDwDIDZUqNHEVHWbk=; b=UHxqNvgwlrD5lxIwy3reJB/1aPz6Ka8wyAifZ+wbgh4gEIIWpxD5cvtriwPcugFBBH DtqllZu2cGngj5OlQ5M7m7V6BAtGv+tg9tDtM1J+1pOffWoZ/JdfmvSmCSeLsx1R/QKg 9LDug/VV2GDvR91mdNGRxSIzvZaXYaSQqF3GLsAI/NpIjXdR3nrpo33IpSHtOniCSFJ4 6NlYxmxpVO0eeo2VvnO9LLkST0oijJdpoBCT8A7gUEvpIk4koSsmvMOm/+aNgw1cyfLp EmBShDQA2ozNdSQxxvtvLRFP47HX7p50JT24A66nyi+upy6FjrNA3UcY7Bu0fO0bSxrO 9iHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=zeRsPUGVPv9WLg9yQUCp/wsgSGRDwDIDZUqNHEVHWbk=; b=tzDqaQWRsTUbBJ47K/mAo4D69Sau1r8gierDfxVB8p+rAlxtXQ2JbAftcXoJVJnhVe 7gaa4tK/503o9zOmNTN3A7wNyHCX1tIOt87TLIDW5X7t+1J0QbH/qKr3GjKEAzrx8i3P cuScIs54ecJ+eXv01RkQWE3dPCxpbC7OvLn5DX8n58e0jzJMLCh7h6nVJjJorvCgBwSI BfkTc+kS0BeNsYwAdGcW7nXW45aK0YX0TDMxPqxW2nNSttT4IfumXrxnJk6w4u9EN0AP +3VpdvRerZOTn6axr1NlsY5oWjY0bD9r25sd1+/+0Ru6Ig018SFhB1RTaximlGrFKU39 Em9A== X-Gm-Message-State: APt69E3ITbK3d5dpQZbALapYq9Vk+YK0ANzxRxZ02gPpxgQwaedts9Ww CNRwWS3bhFjun5NEz6aazZk= X-Google-Smtp-Source: ADUXVKJ1Pu3pq1wdFx/8bXybMZrrqz4jUXnRasq3u1eQTB30Tx1iUt12+hSgOf3l8l/mNRWgSBJlKA== X-Received: by 2002:adf:bd89:: with SMTP id l9-v6mr12208969wrh.266.1528705135718; Mon, 11 Jun 2018 01:18:55 -0700 (PDT) Received: from localhost (pD9E510DD.dip0.t-ipconnect.de. [217.229.16.221]) by smtp.gmail.com with ESMTPSA id h193-v6sm13814091wmd.25.2018.06.11.01.18.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Jun 2018 01:18:55 -0700 (PDT) From: Thierry Reding To: Michael Turquette , Stephen Boyd Cc: Mikko Perttunen , Dmitry Osipenko , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] clk: tegra: Make vic03 a child of pll_c3 Date: Mon, 11 Jun 2018 10:18:53 +0200 Message-Id: <20180611081853.31474-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra124.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 0c69c7970950..f5048f82c0b9 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -1290,6 +1290,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { { TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 }, { TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 }, { TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 }, + { TEGRA124_CLK_VIC03, TEGRA124_CLK_PLL_C3, 0, 0 }, /* must be the last entry */ { TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 }, };